公开(公告)号：US07303663B2

公开(公告)日：2007-12-04

申请号：US10434497

申请日：2003-05-07

Applicant: Adam L. Cohen ,  Michael S. Lockard ,  Dale S. McPherson

Inventor： Adam L. Cohen ,  Michael S. Lockard ,  Dale S. McPherson

IPC: C25D5/02 ,  C25D5/10 ,  C25D5/12 ,  C25D5/48 ,  C25D5/52

CPC classification number: B81C1/00126 ,  B33Y10/00 ,  B33Y70/00 ,  B81B2201/042 ,  B81C1/00476 ,  B81C2201/014 ,  C23C18/1605 ,  C23C18/1651 ,  C25D1/003 ,  G01P15/0802 ,  G01P15/125 ,  H01P1/202 ,  H01P3/06 ,  H01P5/183 ,  H01P11/00 ,  H01P11/005 ,  H05K3/4647

Abstract: Multilayer structures are electrochemically fabricated from at least one structural material (e.g. nickel), that is configured to define a desired structure and which may be attached to a substrate, and from at least one sacrificial material (e.g. copper) that surrounds the desired structure. After structure formation, the sacrificial material is removed by a multi-stage etching Operation. In some embodiments sacrificial material to be removed may be located within passages or the like on a substrate or within an add-on component. The multi-stage etching Operations may be separated by intermediate post processing activities, they may be separated by cleaning Operations, or barrier material removal Operations, or the like. Barriers may be fixed in position by contact with structural material or with a substrate or they may be solely fixed in position by sacrificial material and are thus free to be removed after all retaining sacrificial material is etched.

Abstract translation: 多层结构由至少一种结构材料（例如镍）进行电化学制造，其被构造成限定期望的结构并且可以附着到基底上，并且由至少一种围绕期望结构的牺牲材料（例如铜）制成。 在结构形成之后，通过多级蚀刻操作去除牺牲材料。 在一些实施例中，待移除的牺牲材料可以位于基底上或附加部件内的通道等内。 多级蚀刻操作可以通过中间后处理活动分开，它们可以通过清洁操作或阻隔材料去除操作等分开。 障碍物可以通过与结构材料或基底接触而固定就位，或者它们可以通过牺牲材料单独固定在适当位置，并且因此在所有保留牺牲材料被蚀刻之后可以被自由地去除。

公开(公告)号：US07214324B2

公开(公告)日：2007-05-08

申请号：US11107083

申请日：2005-04-15

Applicant: Dan W. Chilcott

Inventor： Dan W. Chilcott

IPC: C23F1/00

CPC classification number: B81B3/0072 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/0264 ,  B81B2203/0315 ,  B81B2203/0338 ,  B81C2201/0135 ,  B81C2201/014 ,  B81C2201/017

Abstract: A technique for manufacturing a micro-electro mechanical structure includes a number of steps. Initially, a cavity is formed into a first side of a handling wafer, with a sidewall of the cavity forming a first angle greater than about 54.7 degrees with respect to a first side of the handling wafer at an opening of the cavity. Then, a bulk etch is performed on the first side of the handling wafer to modify the sidewall of the cavity to a second angle greater than about 90 degrees, with respect to the first side of the handling wafer at the opening of the cavity. Next, a second side of a second wafer is bonded to the first side of the handling wafer.

Abstract translation: 微电子机械结构的制造技术包括多个步骤。 最初，空腔形成处理晶片的第一侧，空腔的侧壁在空腔的开口处相对于处理晶片的第一侧形成大于约54.7度的第一角度。 然后，在处理晶片的第一侧上执行体蚀刻，以将空腔的侧壁相对于处理晶片在空腔开口处的第一侧大于约90度的第二角度进行修改。 接下来，将第二晶片的第二面接合到处理晶片的第一侧。

公开(公告)号：US20060264014A1

公开(公告)日：2006-11-23

申请号：US11335162

申请日：2006-01-18

Applicant: Robert Bower

Inventor： Robert Bower

IPC: H01L27/12 ,  H01L21/30 ,  H01L21/425

CPC classification number: B81C99/008 ,  B81C1/00595 ,  B81C2201/014 ,  B81C2201/019

Abstract: A material having a top portion (active layer) of a thickness and other characteristics optimized for formation of a desired nanostructure, followed by an insulator layer (intermediate or boundary layer) chosen for its electrical insulation and etch resistance from a substrate material formed adjacent to it such that after subsequent processing the substrate may be removed by polishing and etching to leave the nanostructure processed top layer as a thin layer bonded to a 3-d stack or other structure as a thin layer. Thus, the substrate layer has been optimized to have a very high etch rate and to have a large difference in its etch rate and that of the intermediate insulator layer so that it can be selectively etched.

Abstract translation: 一种具有厚度的顶部（活性层）和为了形成期望的纳米结构而优化的其它特性的材料，其后是绝缘体层（中间层或边界层） 使得在后续处理之后，可以通过抛光和蚀刻去除衬底，以将纳米结构处理的顶层作为薄层结合到作为薄层的3-d叠层或其它结构的薄层。 因此，衬底层已经被优化以具有非常高的蚀刻速率，并且其蚀刻速率和中间绝缘体层的蚀刻速率差异很大，从而可以选择性地蚀刻。

公开(公告)号：US07128843B2

公开(公告)日：2006-10-31

申请号：US10786824

申请日：2004-02-24

Applicant: Sarabjit Mehta

Inventor： Sarabjit Mehta

IPC: H01L21/00

CPC classification number: B81C1/00158 ,  B81C2201/014 ,  Y10T428/24479 ,  Y10T428/2462

Abstract: A process for fabricating monolithic membrane structures having air gaps is disclosed, comprising the steps of: providing a wafer; depositing and patterning a protective layer on the wafer; providing a trench in the wafer; depositing and patterning a metal in the trench; depositing and patterning a sacrificial layer on the metal; depositing and patterning a membrane pad on the sacrificial layer; providing a polymeric film on the protective layer and sacrificial layer, wherein part of the polymeric film has a tensile stress; and releasing part of the polymeric film from the protective layer and sacrificial layer, wherein the tensile stress of a portion of the polymeric film releases the portion of the polymeric film from the wafer and generates the air gap.

公开(公告)号：US20060234042A1

公开(公告)日：2006-10-19

申请号：US11318714

申请日：2005-12-27

Applicant: Rui Yang ,  Nathan Kreutter ,  Nanyakkara Somasiri

Inventor： Rui Yang ,  Nathan Kreutter ,  Nanyakkara Somasiri

IPC: B32B7/12 ,  B32B3/00

CPC classification number: B81C1/00071 ,  B01L3/502707 ,  B01L2200/12 ,  B01L2300/0645 ,  B01L2300/0816 ,  B01L2300/12 ,  B01L2400/0415 ,  B01L2400/086 ,  B81B2201/058 ,  B81C2201/014 ,  Y10T428/24917 ,  Y10T428/2804

Abstract: An etched dielectric film having an adhered etch stop layer for use in microfluidic devices. Channels, recesses, and other features can be etched into the films to make them suitable for use in microfluidic devices.

Abstract translation: 具有用于微流体装置的粘附蚀刻停止层的蚀刻电介质膜。 可以将通道，凹槽和其它特征蚀刻到膜中，使其适用于微流体装置。

公开(公告)号：US20050266598A1

公开(公告)日：2005-12-01

申请号：US11134521

申请日：2005-05-23

Applicant: Jong-pal Kim ,  Sang-woo Lee ,  Byeung-Leul Lee

Inventor： Jong-pal Kim ,  Sang-woo Lee ,  Byeung-Leul Lee

IPC: B81B3/00 ,  B81C1/00 ,  G01P15/08 ,  G01P15/125 ,  G02B26/08 ,  H01L21/00

CPC classification number: B81C1/00626 ,  B81B2201/0235 ,  B81B2201/0242 ,  B81B2201/045 ,  B81B2203/0109 ,  B81B2203/0118 ,  B81C2201/014 ,  G01P15/0802 ,  G01P15/125 ,  G02B26/0841

Abstract: A method for fabricating a vertical offset structure that forms a complete vertical offset on a wafer includes a first trench forming step of forming first trenches on a wafer; a first etching step of performing a first patterning for determining etching positions of second and third trenches by depositing a first thin film on the wafer, performing a second patterning for temporarily protecting the etching position of the third trench by depositing a second thin film on the first thin film and the wafer, and then forming the second trenches by etching the wafer; a second etching step of forming a protection layer on side surfaces of the second trenches and then vertically extending the second trenches by etching the wafer; a third etching step of removing the second thin film and then forming the third trench by etching a position from which the second thin film is removed; and a fourth etching step of horizontally extending the second trenches vertically extended at the second etching step and the third trench by etching the wafer.

Abstract translation: 用于制造在晶片上形成完整的垂直偏移的垂直偏移结构的方法包括在晶片上形成第一沟槽的第一沟槽形成步骤; 第一蚀刻步骤，通过在晶片上沉积第一薄膜来执行用于确定第二和第三沟槽的蚀刻位置的第一图案化，执行用于暂时保护第三沟槽的蚀刻位置的第二图案化， 第一薄膜和晶片，然后通过蚀刻晶片形成第二沟槽; 第二蚀刻步骤，在所述第二沟槽的侧表面上形成保护层，然后通过蚀刻所述晶片垂直延伸所述第二沟槽; 第三蚀刻步骤，通过蚀刻除去第二薄膜的位置来去除第二薄膜，然后形成第三沟槽; 以及第四蚀刻步骤，通过蚀刻晶片水平延伸在第二蚀刻步骤和第三沟槽处垂直延伸的第二沟槽。

公开(公告)号：US20050130351A1

公开(公告)日：2005-06-16

申请号：US10766557

申请日：2004-01-27

Applicant: Glenn Leedy

Inventor： Glenn Leedy

IPC: B81B3/00 ,  G02F1/13 ,  G03F7/20 ,  G11C29/00 ,  H01L21/762 ,  H01L21/764 ,  H01L21/98 ,  H01L23/48 ,  H01L23/538 ,  H01L25/065 ,  H01L21/82

CPC classification number: H01L25/50 ,  B81B2203/0127 ,  B81B2207/07 ,  B81C1/00246 ,  B81C2201/014 ,  B81C2203/075 ,  G02F1/13452 ,  G02F2001/136281 ,  G03F7/70658 ,  G11C29/006 ,  H01L21/762 ,  H01L21/76264 ,  H01L21/76289 ,  H01L21/764 ,  H01L23/481 ,  H01L23/538 ,  H01L23/5381 ,  H01L23/5383 ,  H01L23/5386 ,  H01L23/5387 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/01019 ,  H01L2924/0102 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/15165 ,  H01L2924/15312 ,  H01L2924/3011 ,  H01L2924/3025 ,  Y10S438/949 ,  H01L2924/00

Abstract: General purpose methods for the fabrication of integrated circuits from flexible membranes formed of very thin low stress dielectric materials, such as silicon dioxide or silicon nitride, and semiconductor layers. Semiconductor devices are formed in a semiconductor layer of the membrane. The semiconductor membrane layer is initially formed from a substrate of standard thickness, and all but a thin surface layer of the substrate is then etched or polished away. In another version, the flexible membrane is used as support and electrical interconnect for conventional integrated circuit die bonded thereto, with the interconnect formed in multiple layers in the membrane. Multiple die can be connected to one such membrane, which is then packaged as a multi-chip module. Other applications are based on (circuit) membrane processing for bipolar and MOSFET transistor fabrication, low impedance conductor interconnecting fabrication, flat panel displays, maskless (direct write) lithography, and 3D IC fabrication.

Abstract translation: 由非常薄的低应力电介质材料（例如二氧化硅或氮化硅）和半导体层形成的柔性膜制造集成电路的通用方法。 半导体器件形成在膜的半导体层中。 半导体膜层最初由标准厚度的衬底形成，然后将衬底的薄表面层全部蚀刻或抛光。 在另一个版本中，柔性膜用作与其连接的常规集成电路管芯的支撑和电互连，其中互连在膜中形成多层。 多个管芯可以连接到一个这样的膜，然后将其封装成多芯片模块。 其他应用基于用于双极和MOSFET晶体管制造，低阻抗导体互连制造，平板显示器，无掩模（直写））光刻和3D IC制造的（电路）膜处理。

公开(公告)号：US20040155306A1

公开(公告)日：2004-08-12

申请号：US10773312

申请日：2004-02-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

IPC: H01L027/14

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

Abstract translation: 一种用于制造具有固定到基板上的固定部件，连接部件，驱动部件，驱动电极和接触部件的MEMS器件的方法，包括在所述基板上图形化所述驱动电极; 在所述基板上形成绝缘层; 图案化绝缘层并蚀刻绝缘层的固定区域和接触区域; 在衬底上形成金属层; 使金属层平坦化直到绝缘层露出; 在所述基板上形成牺牲层; 图案化牺牲层以形成露出固定区域中绝缘层和金属层的一部分的开口; 在所述牺牲层上形成MEMS结构层以部分地填充所述开口，从而在其中形成侧壁; 并且通过蚀刻选择性地去除牺牲层的一部分，使得牺牲层的一部分保留在固定区域中。

公开(公告)号：US06720201B2

公开(公告)日：2004-04-13

申请号：US10384495

申请日：2003-03-10

Applicant: Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

Inventor： Eun-sung Lee ,  Chung-woo Kim ,  In-sang Song ,  Jong-seok Kim ,  Moon-chul Lee

IPC: H01L2100

CPC classification number: B81B3/0078 ,  B81B2201/014 ,  B81B2203/0118 ,  B81B2203/0307 ,  B81B2203/04 ,  B81C2201/0107 ,  B81C2201/014 ,  H01H59/0009

Abstract: A method for fabricating a MEMS device having a fixing part fixed to a substrate, a connecting part, a driving part, a driving electrode, and contact parts, includes patterning the driving electrode on the substrate; forming an insulation layer on the substrate; patterning the insulation layer and etching a fixing region and a contact region of the insulation layer; forming a metal layer over the substrate; planarizing the metal layer until the insulation layer is exposed; forming a sacrificial layer on the substrate; patterning the sacrificial layer to form an opening exposing a portion of the insulation layer and the metal layer in the fixing region; forming a MEMS structure layer on the sacrificial layer to partially fill the opening, thereby forming sidewalls therein; and selectively removing a portion of the sacrificial layer by etching so that a portion of the sacrificial layer remains in the fixing region.

公开(公告)号：US06565765B1

公开(公告)日：2003-05-20

申请号：US09598543

申请日：2000-06-21

Applicant: Heribert Weber

Inventor： Heribert Weber

IPC: B44C122

CPC classification number: B81C1/00158 ,  B81C2201/014 ,  B81C2201/0178 ,  G01F1/6845

Abstract: In a method for manufacturing a sensor having a membrane, a silicon nitride layer is deposited on the upper side of a silicon substrate. For that, an LPCVD or PECVD process is used. From the lower side of the silicon substrate, an opening is etched in which ends at the lower side of the silicon nitride layer.

Abstract translation: 在制造具有膜的传感器的方法中，在硅衬底的上侧淀积氮化硅层。 为此，使用LPCVD或PECVD工艺。 从硅衬底的下侧开始，在氮化硅层的下侧蚀刻开口。