Abstract:
An electrically insulating sheathing for a piezoresistor and a semiconductor material are provided such that the piezoresistor is able to be used in the high temperature range, e.g., for measurements at higher ambient temperatures than 200° C. A doped resistance area is initially laterally delineated by at least one circumferential essentially vertical trench and is undercut by etching over the entire area. An electrically insulating layer is then created on the wall of the trench and the undercut area, so that the resistance area is electrically insulated from the adjacent semiconductor material by the electrically insulating layer.
Abstract:
A method is described for creating at least one recess in a semiconductor component, in particular a micromechanical or electrical semiconductor component, having the following steps: applying at least one mask to the semiconductor component, forming at least one lattice having at least one or more lattice openings in the mask over the recess to be formed, the lattice opening or lattice openings being formed as a function of the etching rate and/or the dimensioning of the recess to be formed; forming the recess below the lattice.
Abstract:
A method for manufacturing a micromechanical structure includes: forming a first insulation layer above a substrate; forming a first micromechanical functional layer on the first insulation layer; forming multiple first trenches in the first micromechanical functional layer, which trenches extend as far as the first insulation layer; forming a second insulation layer on the first micromechanical functional layer, which second insulation layer fills up the first trenches; forming etch accesses in the second insulation layer, which etch accesses locally expose the first micromechanical functional layer; and etching the first micromechanical functional layer through the etch accesses, the filled first trenches and the first insulation layer acting as an etch stop.
Abstract:
A method for providing and connecting a first contact area to at least one second contact area on a substrate, in particular in the case of a semiconductor component, which includes providing at least one insulation layer on the substrate, forming an opening in the at least one insulation layer over at least one insulation trench of a first contact area, applying at least one metal layer to the insulation layer, forming the first and second contact areas in the at least one metal layer and at least one printed conductor between the two contact areas, and forming the insulation trench.
Abstract:
A method is described for filling cavities in wafers, the cavities being open to a predetermined surface of the wafer, including the following steps: applying a lacquer-like filling material to the predetermined surface of the wafer; heating the wafer at a first temperature; driving out gas bubbles enclosed in the filling material by heating the wafer under vacuum at a second temperature which is equal to or higher than the first temperature; and curing the filling material by heating the wafer at a third temperature which is higher than the second temperature. Furthermore, also described is a blind hole filled using such a method and general 3D cavities as well as a wafer having insulation trenches of a silicon via filled using such a method.
Abstract:
A micromechanical acceleration sensor for a transport device, in particular a motor vehicle, having a seismic mass. The seismic mass includes an auxiliary mass, and the auxiliary mass is composed of a different material than the seismic mass. Also described is a method for manufacturing an acceleration sensor for a transport device, in particular a motor vehicle, having a seismic mass, an auxiliary mass being provided on/in the seismic mass when forming the seismic mass. Also described is an assembly, apparatus, or device, in particular for a motor vehicle. The assembly, apparatus, or device has a micromechanical acceleration sensor as described, or an acceleration sensor manufactured as described.
Abstract:
A micromechanical component is described which includes a substrate; a monocrystalline layer, which is provided above the substrate and which has a membrane area; a cavity that is provided underneath the membrane area; and one or more porous areas, which are provided inside the monocrystalline layer and which have a doping that is higher than that of the surrounding layer.
Abstract:
A method for manufacturing a micromechanical component is proposed. In this context, at least one trench structure having a depth less than the substrate thickness is to be produced in a substrate. In addition, an insulating layer and a filler layer are produced or applied on a first side of the substrate. The filler layer comprises a filler material that substantially fills up the trench structure. A planar first side of the substrate is produced by way of a subsequent planarization within a plane of the filler layer or of the insulating layer or of the substrate. A further planarization of the second side of the substrate is then accomplished. A micromechanical component that is manufactured in accordance with the method is also described.
Abstract:
A method for producing a micromechanical component is proposed, a trench structure being substantially completely filled up by a first filler layer, and a first mask layer being applied on the first filler layer, on which in turn a second filler layer and a second mask layer are applied. A micromechanical component is also proposed, the first filler layer filling up the trench structure of the micromechanical component and at the same time forming a movable sensor structure.
Abstract:
A method for manufacturing a diaphragm, on a semiconductor substrate, includes the method operations or tasks of a) providing a semiconductor substrate, b) producing trenches in the semiconductor substrate, webs made of semiconductor substrate remaining between the trenches, c) producing an oxide layer on the walls of the trenches with the aid of a thermal oxidation method, d) producing access openings in a cover layer produced in a preceding method operation or task on the semiconductor substrate, to expose the semiconductor substrate in the area of the webs, e) isotropic etching of the semiconductor substrate exposed in method operation or task d) using a method selective to the oxide layer and to the cover layer, at least one cavity being produced in the webs below the cover layer, which is laterally delimited by the oxide layer of at least one trench, and f) depositing a sealing layer to seal the access openings in the cover layer.