公开(公告)号：US09437427B1

公开(公告)日：2016-09-06

申请号：US14984546

申请日：2015-12-30

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Lukas Czornomaz ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/02 ,  H01L21/306 ,  H01L21/308

CPC classification number: H01L21/02645 ,  H01L21/02164 ,  H01L21/02236 ,  H01L21/02255 ,  H01L21/0245 ,  H01L21/02488 ,  H01L21/02538 ,  H01L21/02609 ,  H01L21/02639 ,  H01L21/02647 ,  H01L21/30604 ,  H01L21/30612 ,  H01L21/308 ,  H01L21/31116 ,  H01L21/322 ,  H01L21/8258 ,  H01L21/84 ,  H01L27/1203

Abstract: After oxidizing a sacrificial semiconductor layer composed of silicon germanium that is located over an insulator layer to form a germanium-enriched region located within a first end of the sacrificial semiconductor layer and having a greater germanium concentration than a remaining portion of the sacrificial semiconductor layer, the remaining portion of the sacrificial semiconductor layer is removed to provide a trench. Next, a semiconductor barrier layer is formed on a sidewall of the germanium-enriched region that is exposed by the trench. A III-V compound semiconductor layer is formed within the trench by a lateral epitaxial semiconductor regrowth process.

Abstract translation: 在氧化由位于绝缘体层之上的硅锗构成的牺牲半导体层之后，形成位于牺牲半导体层的第一端内并具有比牺牲半导体层的剩余部分更大的锗浓度的富锗区， 去除牺牲半导体层的剩余部分以提供沟槽。 接下来，在由沟槽暴露的富锗区域的侧壁上形成半导体阻挡层。 通过横向外延半导体再生长工艺在沟槽内形成III-V族化合物半导体层。

公开(公告)号：US09425291B1

公开(公告)日：2016-08-23

申请号：US14964122

申请日：2015-12-09

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L29/06 ,  H01L29/66 ,  H01L27/088 ,  H01L29/78 ,  H01L29/10 ,  H01L29/423 ,  H01L29/40 ,  H01L29/32

CPC classification number: H01L29/0676 ,  B82Y10/00 ,  H01L21/823412 ,  H01L21/8252 ,  H01L21/8258 ,  H01L27/088 ,  H01L27/0886 ,  H01L29/045 ,  H01L29/0673 ,  H01L29/1037 ,  H01L29/20 ,  H01L29/32 ,  H01L29/401 ,  H01L29/41733 ,  H01L29/42356 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66795 ,  H01L29/775 ,  H01L29/7853

Abstract: A semiconductor structure is provided that includes a plurality of suspended and stacked nanosheets of semiconductor channel material located above a pillar of a sacrificial III-V compound semiconductor material. Each semiconductor channel material comprises a semiconductor material that is substantially lattice matched to, but different from, the sacrificial III-V compound semiconductor material, and each suspended and stacked nanosheets of semiconductor channel material has a chevron shape. A functional gate structure can be formed around each suspended and stacked nanosheet of semiconductor channel material.

Abstract translation: 提供一种半导体结构，其包括位于牺牲III-V族化合物半导体材料的柱上方的多个悬置和堆叠的半导体沟道材料的纳米片。 每个半导体沟道材料包括与牺牲III-V化合物半导体材料基本上晶格匹配但不同的半导体材料，并且半导体沟道材料的每个悬置和堆叠的纳米片具有人字形。 可以在半导体通道材料的每个悬挂和堆叠的纳米片周围形成功能栅极结构。

公开(公告)号：US09406748B1

公开(公告)日：2016-08-02

申请号：US14947444

申请日：2015-11-20

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Bruce B. Doris ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/336 ,  H01L29/06 ,  H01L29/40 ,  H01L29/66 ,  H01L21/84 ,  H01L27/12 ,  H01L29/423 ,  H01L21/02 ,  H01L21/3213 ,  H01L21/311

CPC classification number: H01L29/78696 ,  B82Y10/00 ,  H01L21/02636 ,  H01L21/187 ,  H01L21/3086 ,  H01L21/31111 ,  H01L21/32139 ,  H01L21/845 ,  H01L27/1203 ,  H01L27/1211 ,  H01L29/0673 ,  H01L29/401 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/66742 ,  H01L29/6681 ,  H01L29/78681 ,  H01L29/78684

Abstract: A fin stack structure is provided on an insulator layer. The fin stack structure comprises, from bottom to top, a first semiconductor fin portion, a dielectric fin portion, a second semiconductor fin portion and a hard mask fin portion. A sacrificial gate structure is formed on a portion of the fin stack structure. The hard mask fin portion and the dielectric fin portion not located beneath the sacrificial gate structure are removed. An epitaxial semiconductor material structure is then formed from exposed surfaces of each semiconductor fin portion. The sacrificial gate structure is then removed. Next, remaining portions of the hard mask fin portion and the dielectric fin portion are removed. The insulating layer is then recessed. After recessing the insulator layer, the first and second semiconductor fin portions are suspended and are stacked one atop the other.

Abstract translation: 在绝缘体层上设置鳍片堆叠结构。 翅片堆叠结构从底部到顶部包括第一半导体翅片部分，介电翅片部分，第二半导体翅片部分和硬掩模翅片部分。 牺牲栅极结构形成在鳍片堆叠结构的一部分上。 除去不在牺牲栅极结构下方的硬掩模翅片部分和介电鳍片部分。 然后从每个半导体鳍部分的暴露表面形成外延半导体材料结构。 然后去除牺牲栅极结构。 接下来，去除硬掩模翅片部分和介电片部分的剩余部分。 绝缘层然后凹入。 在使绝缘体层凹陷之后，第一和第二半导体翅片部分被悬置并彼此层叠。

公开(公告)号：US20160197147A1

公开(公告)日：2016-07-07

申请号：US15068601

申请日：2016-03-13

Applicant: International Business Machines Corporation

Inventor： Karthik Balakrishnan ,  John Bruley ,  Pouya Hashemi ,  Ali Khakifirooz ,  John A. Ott ,  Alexander Reznicek

IPC: H01L29/161 ,  H01L29/10 ,  H01L27/088 ,  H01L29/06

CPC classification number: H01L29/161 ,  H01L21/18 ,  H01L21/30604 ,  H01L21/31144 ,  H01L21/324 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0657 ,  H01L29/1054 ,  H01L29/66818 ,  H01L29/785

Abstract: Thermal condensation is employed to obtain a finned structure including strained silicon germanium fins having vertical side walls and a germanium content that may be high relative to silicon. A hard mask is used directly on a low-germanium content silicon germanium layer. The hard mask is patterned and fins are formed beneath the hard mask from the silicon germanium layer. Thermal condensation in an oxidizing ambient causes the formation of regions beneath the hard mask that have a high germanium content. The hard mask is trimmed to a target critical dimension. The regions beneath the hard mask and adjoining oxide material are subjected to reactive ion etch, resulting in the formation of high-germanium content fins with planar, vertically extending sidewalls.

Abstract translation: 使用热凝结来获得包括具有垂直侧壁的应变硅锗翅片和相对于硅可能高的锗含量的翅片结构。 硬掩模直接用于低锗含量的硅锗层上。 硬掩模被图案化，并且翅片从硬质掩模形成在硅锗层的下方。 在氧化环境中的热凝结导致形成具有高锗含量的硬掩模下面的区域。 硬面罩被修剪到目标临界尺寸。 硬掩模和毗邻的氧化物材料之下的区域经受反应离子蚀刻，导致形成具有平面的垂直延伸的侧壁的高锗含量的翅片。

公开(公告)号：US20240127097A1

公开(公告)日：2024-04-18

申请号：US18046470

申请日：2022-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Abram L. Falk ,  Martin O. Sandberg ,  Karthik Balakrishnan ,  Oliver Dial ,  Jason S. Orcutt

IPC: G06N10/40

CPC classification number: G06N10/40

Abstract: Methods and systems for mitigating the effects of defects in a quantum processor are provided. A mitigation system uses an iterative process of applying light pulses and examining qubit relaxation times to eliminate or minimize two-level system (TLS) interaction with qubits. The system applies a first light pulse to illuminate a quantum processor having one or more qubits. The system receives qubit relaxation times that are measured at different electric field frequencies after applying the first light pulse. The system applies a second light pulse to illuminate the quantum processor upon determining that the received qubit relaxation times indicates presence of a strongly coupled TLS in the quantum processor

公开(公告)号：US11362086B2

公开(公告)日：2022-06-14

申请号：US16739853

申请日：2020-01-10

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L27/07 ,  H01L29/66 ,  H01L29/78 ,  H01L29/861 ,  H01L29/739 ,  H01L21/8234 ,  G11C7/06 ,  G11C11/4091

Abstract: An electrical device including a vertical transistor device connected to a vertical diode. The vertical diode connected transistor device including a vertically orientated channel. The vertical diode connected transistor device also includes a first diode source/drain region provided by an electrically conductive surface region of a substrate at a first end of the diode vertically orientated channel, and a second diode source/drain region present at a second end of the vertically orientated channel. The vertical diode also includes a diode gate structure in electrical contact with the first diode source/drain region.

公开(公告)号：US11271108B2

公开(公告)日：2022-03-08

申请号：US16843607

申请日：2020-04-08

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Karthik Balakrishnan

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/66 ,  H01L29/423

Abstract: A Vertical Function Field Effect Transistor (VIFET) is disclosed with reduced noise and input capacitance and high input impedance. The VIFET has a substrate; a source disposed on the substrate; a drain, and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 am and 10 om, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.

公开(公告)号：US20210320205A1

公开(公告)日：2021-10-14

申请号：US16843607

申请日：2020-04-08

Applicant: International Business Machines Corporation

Inventor： Bahman Hekmatshoartabari ,  Alexander Reznicek ,  Karthik Balakrishnan

IPC: H01L29/78 ,  H01L29/786 ,  H01L29/423 ,  H01L29/66

Abstract: A Vertical Junction Field Effect Transistor (VJFET) is disclosed with reduced noise and input capacitance and high input impedance. The VJFET has a substrate; a source disposed on the substrate; a drain; and a channel. The vertical channel has one or more channel sidewall surfaces. The channel sidewall surfaces have a total or aggregate channel sidewall surface area. A semiconductor gate grown on one or more of the channel sidewall surfaces has a thickness below 10 nanometers (nm), or between 3 nm and 10 nm, that reduces transistor noise. The interface surface area between the conductive (e.g. metal) external electrical gate contact and the contacted surface of the semiconductor gate is minimized to further reduce transistor noise.

公开(公告)号：US11145816B2

公开(公告)日：2021-10-12

申请号：US16723217

申请日：2019-12-20

Applicant: International Business Machines Corporation

Inventor： Alexander Reznicek ,  Bahman Hekmatshoartabari ,  Takashi Ando ,  Karthik Balakrishnan

IPC: H01L27/24 ,  H01L45/00

Abstract: A one-transistor-two-resistor (1T2R) resistive random access memory (ReRAM) structure, and a method for forming the same, includes forming a vertical field effect transistor (VFET) including an epitaxial region located above a channel region and below a dielectric cap. The epitaxial region includes two opposing protruding regions of triangular shape bounded by planes that extend horizontally beyond the channel region. A ReRAM stack is conformally deposited on the VFET. The ReRAM stack includes an oxide layer located directly above the epitaxial region, a top electrode layer directly above the oxide layer and a metal fill above the top electrode layer. Each of the two opposing protruding regions of the epitaxial region acts as a bottom electrode for the ReRAM stack.

公开(公告)号：US11043587B2

公开(公告)日：2021-06-22

申请号：US15783749

申请日：2017-10-13

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Karthik Balakrishnan ,  Kangguo Cheng ,  Pouya Hashemi ,  Alexander Reznicek

IPC: H01L21/82 ,  H01L29/78 ,  H01L29/10 ,  H01L29/165 ,  H01L27/088 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/02 ,  H01L21/762 ,  H01L29/161 ,  H01L27/082

Abstract: A vertical fin field effect transistor including a doped region in a substrate, wherein the doped region has the same crystal orientation as the substrate, a first portion of a vertical fin on the doped region, wherein the first portion of the vertical fin has the same crystal orientation as the substrate and a first portion width, a second portion of the vertical fin on the first portion of the vertical fin, wherein the second portion of the vertical fin has the same crystal orientation as the first portion of the vertical fin, and the second portion of the vertical fin has a second portion width less than the first portion width, a gate structure on the second portion of the vertical fin, and a source/drain region on the top of the second portion of the vertical fin.