公开(公告)号：US09496371B1

公开(公告)日：2016-11-15

申请号：US14877051

申请日：2015-10-07

Applicant: International Business Machines Corporation

Inventor： Russell H. Arndt ,  Hong He ,  Gauri Karve ,  Fee Li Lie ,  Muthumanickam Sankarapandian

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/10 ,  H01L21/31 ,  H01L21/306 ,  H01L21/311 ,  H01L21/32 ,  H01L21/3105 ,  H01L21/02

CPC classification number: H01L29/66795 ,  H01L21/3081

Abstract: A method for protecting channels during fin fabrication. Fins are formed on a substrate. A conformal liner layer (or layers) is applied on the fins. Active portions of a semiconductor device are patterned in the fins using a first organic planarizing material. The first organic planarizing material is stripped. The length of the fins is adjusted using a second organic planarizing material. The second organic planarizing material is stripped. The conformal liner layer(s) is stripped.

Abstract translation: 一种用于在翅片制造期间保护通道的方法。 翅片形成在基底上。 在翅片上施加保形衬层（或层）。 半导体器件的有源部分使用第一有机平面化材料在散热片中图案化。 剥离第一有机平面化材料。 使用第二有机平面化材料调节翅片的长度。 剥离第二有机平面化材料。 剥去保形衬垫层。

公开(公告)号：US09496281B2

公开(公告)日：2016-11-15

申请号：US15082199

申请日：2016-03-28

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L21/00 ,  H01L27/12 ,  H01L27/092 ,  H01L29/10 ,  H01L29/161 ,  H01L29/165 ,  H01L29/06 ,  H01L21/027 ,  H01L21/02 ,  H01L21/3105 ,  H01L21/311 ,  H01L21/306 ,  H01L21/8238 ,  H01L29/66 ,  H01L21/84

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

Abstract translation: 一种在包括p型场效应晶体管器件（pFET）和n型场效应晶体管（nFET）器件的双隔离互补金属氧化物半导体（CMOS）器件中形成鳍片的方法和具有 描述了双重隔离。 CMOS器件包括n型场效应晶体管（nFET）区域，nFET区域包括由应变硅组成的一个或多个鳍片，nFET区域中的一个或鳍形成在绝缘体上。 CMOS器件还包括p型场效应晶体管（pFET）区域，pFET区域包括在外延生长的硅上包括硅（Si）或硅锗（SiGe）的一个或多个鳍，并且包括浅沟槽隔离（STI） 填充以将pFET区域中的一个或多个翅片彼此隔离。

公开(公告)号：US20160329415A1

公开(公告)日：2016-11-10

申请号：US15214851

申请日：2016-07-20

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Junli Wang ,  Yongan Xu ,  Yunpeng Yin

IPC: H01L29/66 ,  H01L21/762 ,  H01L21/311 ,  H01L29/78 ,  H01L29/423 ,  H01L21/02 ,  H01L29/40 ,  H01L29/06

CPC classification number: H01L29/66795 ,  H01L21/02115 ,  H01L21/02274 ,  H01L21/28088 ,  H01L21/31122 ,  H01L21/76224 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/401 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/785

Abstract: A method of forming a semiconductor device that includes forming a sacrificial gate structure on a channel portion of a fin structure, wherein the angle at the intersection of the sidewall of the sacrificial gate structure and an upper surface of the channel portion of the fin structure is obtuse. Epitaxial source and drain region structures are formed on a source region portion and a drain region portion of the fin structure. At least one dielectric material is formed on the sidewall of the sacrificial gate structure. The sacrificial gate structure may be removed to provide an opening to the channel portion of the fin structure. A function gate structure is formed in the opening. At least one angle defined by the intersection of a sidewall of the functional gate structure and an upper surface of the channel portion of the fin structure is obtuse.

公开(公告)号：US20160315049A1

公开(公告)日：2016-10-27

申请号：US14694306

申请日：2015-04-23

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Hong He ,  Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L23/525 ,  H01L29/78 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3065 ,  H01L21/324 ,  H01L21/76897 ,  H01L21/845 ,  H01L23/5256 ,  H01L27/1211 ,  H01L29/66545 ,  H01L29/785

Abstract: An e-Fuse structure is provided on a surface of an insulator layer of a semiconductor-on-insulator substrate (SOI). The e-Fuse structure includes a first metal semiconductor alloy structure of a first thickness, a second metal semiconductor alloy structure of the first thickness, and a metal semiconductor alloy fuse link is located laterally between and connected to the first and second metal semiconductor alloy structures. The metal semiconductor alloy fuse link has a second thickness that is less than the first thickness.

Abstract translation: 在绝缘体上半导体衬底（SOI）的绝缘体层的表面上设置电子保险丝结构。 e熔丝结构包括第一厚度的第一金属半导体合金结构，第一厚度的第二金属半导体合金结构和金属半导体合金熔断体横向位于第一和第二金属半导体合金结构之间并连接到第一和第二金属半导体合金结构 。 金属半导体合金熔断体具有小于第一厚度的第二厚度。

公开(公告)号：US20160293704A1

公开(公告)日：2016-10-06

申请号：US14672311

申请日：2015-03-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Kangguo Cheng ,  Ramachandra Divakaruni ,  Hong He ,  Juntao Li

IPC: H01L29/10 ,  H01L21/28 ,  H01L29/161 ,  H01L29/78

CPC classification number: H01L29/1054 ,  H01L21/28026 ,  H01L21/28158 ,  H01L29/045 ,  H01L29/161 ,  H01L29/165 ,  H01L29/267 ,  H01L29/78 ,  H01L29/785 ,  H01L29/7851

Abstract: A semiconductor structure includes a material stack located on a surface of a semiconductor substrate. The material stack includes, from bottom to top, a silicon germanium alloy portion that is substantially relaxed and defect-free and a semiconductor material pillar that is defect-free. A dielectric material structure surrounds sidewalls of the material stack and is present on exposed portions of the semiconductor substrate.

Abstract translation: 半导体结构包括位于半导体衬底表面上的材料堆叠。 材料堆叠从底部到顶部包括基本上松弛和无缺陷的硅锗合金部分和无缺陷的半导体材料柱。 介电材料结构围绕材料堆叠的侧壁并存在于半导体衬底的暴露部分上。

公开(公告)号：US20160247677A1

公开(公告)日：2016-08-25

申请号：US14628375

申请日：2015-02-23

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/02 ,  H01L27/12

CPC classification number: H01L21/02636 ,  H01L21/02381 ,  H01L21/02488 ,  H01L21/02532 ,  H01L21/0259 ,  H01L21/02639 ,  H01L27/1211 ,  H01L29/161 ,  H01L29/785

Abstract: A method of forming semiconductor fins includes forming a plurality of sacrificial template fins from a first semiconductor material; epitaxially growing fins of a second semiconductor material on exposed sidewall surfaces of the sacrificial template fins; and removing the plurality of sacrificial template fins.

公开(公告)号：US09401372B1

公开(公告)日：2016-07-26

申请号：US14618442

申请日：2015-02-10

Applicant: International Business Machines Corporation

Inventor： Bruce B. Doris ,  Hong He ,  Ali Khakifirooz ,  Junli Wang

IPC: H01L21/00 ,  H01L27/12 ,  H01L21/84 ,  H01L21/762 ,  H01L21/02 ,  H01L21/306 ,  H01L21/311 ,  H01L21/027 ,  H01L21/3105 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/1207 ,  H01L21/02532 ,  H01L21/3086 ,  H01L21/76283 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/845 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/0653 ,  H01L29/1054 ,  H01L29/161 ,  H01L29/165 ,  H01L29/66795

Abstract: A method of forming fins in a dual isolation complimentary-metal-oxide-semiconductor (CMOS) device that includes a p-type field effect transistor device (pFET) and an n-type field effect transistor (nFET) device and a CMOS device with dual isolation are described. The CMOS device includes an n-type field effect transistor (nFET) region, the nFET region including one or more fins comprised of strained silicon, the one or fins in the nFET region being formed on an insulator. The CMOS device also includes a p-type field effect transistor (pFET) region, the pFET region including one or more fins comprised of silicon (Si) or silicon germanium (SiGe) on epitaxially grown silicon and including a shallow trench isolation (STI) fill to isolate the one or more fins of the pFET region from each other.

公开(公告)号：US20160190285A1

公开(公告)日：2016-06-30

申请号：US14585572

申请日：2014-12-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce B. Doris ,  Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L29/66 ,  H01L29/06 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/0653 ,  H01L29/7843 ,  H01L29/7849 ,  H01L29/785

Abstract: Embodiments are directed to a method of enriching and electrically isolating a fin of a FinFET. The method includes forming at least one fin. The method further includes forming under a first set of conditions an enriched upper portion of the at least one fin. The method further includes forming under a second set of conditions an electrically isolated region from a lower portion of the at least one fin, wherein forming under the first set of conditions is spaced in time from forming under the second set of conditions. The method further includes controlling the first set of conditions separately from the second set of conditions.

公开(公告)号：US09379221B1

公开(公告)日：2016-06-28

申请号：US14592042

申请日：2015-01-08

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L21/4763 ,  H01L29/66 ,  H01L29/78 ,  H01L21/321 ,  H01L21/311 ,  H01L21/28

CPC classification number: H01L29/6681 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/32139 ,  H01L29/7851

Abstract: A method of fabricating a replacement metal gate in a transistor device, a fin field effect transistor (finFET), and method of fabricating a finFET device with the replacement metal gate are described. The method of fabricating the replacement metal gate includes forming a dummy gate structure over a substrate, the dummy gate structure being surrounded by an insulating layer, and removing the dummy gate structure so as to expose a trench within the insulating layer. The method also includes conformally depositing a dielectric material layer and a work function metal layer over a the insulating layer and in the trench and removing the dielectric material layer and the work function metal layer from a tip surface of the insulating layer, recessing the work function metal layer below a top of the trench, and selectively forming a gate metal only on exposed surfaces of the work function metal layer.

Abstract translation: 描述了在晶体管器件中制造替代金属栅极的方法，鳍状场效应晶体管（finFET）以及用替换金属栅极制造finFET器件的方法。 制造替代金属栅极的方法包括在衬底上形成虚拟栅极结构，所述虚拟栅极结构被绝缘层包围，并且去除所述伪栅极结构以暴露所述绝缘层内的沟槽。 该方法还包括在绝缘层和沟槽之中共形沉积介电材料层和功函数金属层，并从绝缘层的尖端表面去除介电材料层和功函数金属层，使功函数 金属层，并且仅在功函数金属层的暴露表面上选择性地形成栅极金属。

公开(公告)号：US20160133573A1

公开(公告)日：2016-05-12

申请号：US14538978

申请日：2014-11-12

Applicant: International Business Machines Corporation

Inventor： Hong He ,  Juntao Li ,  Junli Wang ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768

CPC classification number: H01L23/53238 ,  H01L21/76883 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A metal interconnect layer, a method of forming the metal interconnect layer, a method of forming a device that includes the metal interconnect layer are described. The method of forming the metal interconnect layer includes forming an opening in a dielectric layer, forming a metal layer in the opening and over a top surface of the dielectric layer. The method also includes disposing a metal passivation layer on an overburden portion of the metal layer formed over the top surface of the dielectric layer. The metal passivation layer includes a metal selected from a group of: cobalt (Co), ruthenium (Ru), tantalum (Ta), titanium (Ti), nickel (Ni), tungsten (W), any alloy thereof, nitrides of Co, Ru, Ti, Ni, or W, and any combination thereof. The method also includes performing an anneal at a temperature exceeding 100 degrees centigrade and below 300 degrees centigrade.

Abstract translation: 描述金属互连层，形成金属互连层的方法，形成包括金属互连层的器件的方法。 形成金属互连层的方法包括在电介质层中形成开口，在开口中形成金属层，并在电介质层的顶表面上形成金属层。 该方法还包括在形成在电介质层的顶表面上的金属层的覆盖层部分上设置金属钝化层。 金属钝化层包括选自钴（Co），钌（Ru），钽（Ta），钛（Ti），镍（Ni），钨（W），其任何合金，钴的氮化物 ，Ru，Ti，Ni或W及其任意组合。 该方法还包括在超过100摄氏度和低于300摄氏度的温度下进行退火。