公开(公告)号：US09837417B1

公开(公告)日：2017-12-05

申请号：US15378050

申请日：2016-12-14

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L27/092 ,  H01L21/8234 ,  H01L21/225 ,  H01L21/02 ,  H01L27/088 ,  H01L21/8238 ,  H01L29/66

CPC classification number: H01L27/0924 ,  H01L21/02129 ,  H01L21/0217 ,  H01L21/2256 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823828 ,  H01L21/823864 ,  H01L21/823892 ,  H01L27/0886 ,  H01L29/66803

Abstract: A semiconductor device includes a semiconductor substrate having a first region and a second region, a plurality of first semiconductor fins in the first region, a plurality of second semiconductor fins in the second region, a first solid-state dopant source layer within the first region on the semiconductor substrate, a first insulating buffer layer on the first solid-state dopant source layer, a second solid-state dopant source layer within the second region on the semiconductor substrate, a second insulating buffer layer on the second solid-state dopant source layer and on the first insulating buffer layer, a first fin bump in the first region, and a second fin bump in the second region. The first fin bump includes a first sidewall spacer and the second fin bump comprises a second sidewall spacer. The first sidewall spacer has a structure that is different from that of the second sidewall spacer.

公开(公告)号：US09799553B2

公开(公告)日：2017-10-24

申请号：US15469932

申请日：2017-03-27

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/7682 ,  H01L21/31144 ,  H01L21/76802 ,  H01L21/7685 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/53238 ,  H01L23/53295

Abstract: A semiconductor device and a method for manufacturing the same are provided. A semiconductor device includes a substrate, a first capping layer formed above the substrate, a first dielectric layer formed on the first capping layer; a second capping layer formed on the first dielectric layer; a second dielectric layer formed on the second capping layer; a plurality of conducting lines separately formed on the substrate; a third capping layer formed on the conducting lines and the second dielectric layer; and several nano-gaps formed between the adjacent conducting lines, and the nano-gaps being formed in the second dielectric layer, or further extending to the second capping layer or to the first capping layer. The nano-gaps partially open one of the second and first dielectric layers, or the nano-gaps expose the first capping layer or the second capping layer.

公开(公告)号：US20170294539A1

公开(公告)日：2017-10-12

申请号：US15628658

申请日：2017-06-21

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/16 ,  H01L29/66 ,  H01L21/265 ,  H01L21/324 ,  H01L21/02 ,  H01L29/08 ,  H01L29/24

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US20170263504A1

公开(公告)日：2017-09-14

申请号：US15604675

申请日：2017-05-25

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/8234 ,  H01L27/088 ,  H01L29/78 ,  H01L29/66 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/823431 ,  H01L21/3081 ,  H01L21/3085 ,  H01L27/0886 ,  H01L29/0649 ,  H01L29/0688 ,  H01L29/66795 ,  H01L29/785

Abstract: A semiconductor device and a method of forming the same, the semiconductor device includes a substrate, a plurality of fin shaped structures and an insulating layer. The substrate has a fin field-effect transistor (finFET) region, a first region, a second region and a third region. The first region, the second region and the third region have a first surface, a second surface, and a third surface, respectively, where the first surface is relatively higher than the second surface and the second surface is relatively higher than the third surface. The fin shaped structures are disposed on a surface of the fin field-effect transistor region. The insulating layer covers the first surface, the second surface and the third surface.

公开(公告)号：US09748139B1

公开(公告)日：2017-08-29

申请号：US15016230

申请日：2016-02-04

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/768

CPC classification number: H01L21/76897 ,  H01L21/7681 ,  H01L21/76813 ,  H01L21/76816 ,  H01L2221/1021

Abstract: A substrate having thereon a first dielectric layer, a second dielectric layer, and a hard mask layer is provided. A partial via is formed in the second dielectric layer and the hard mask layer. A first photoresist pattern with a first trench opening above the partial via and a second trench opening is formed on the hard mask layer. The hard mask layer and the second dielectric layer are etched through the first trench opening and the second trench opening, thereby forming a first dual damascene structure comprising a first trench and a first via, and a second trench in the second dielectric layer, respectively. A second photoresist pattern having a self-aligned via opening above the second trench is formed. The second dielectric layer is etched through the self-aligned via opening, thereby forming a second dual damascene structure comprising the second trench and a second via under the second trench.

公开(公告)号：US09722093B1

公开(公告)日：2017-08-01

申请号：US15253896

申请日：2016-09-01

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Su Xing ,  Hsueh-Wen Wang ,  Chien-Yu Ko ,  Yu-Cheng Tung ,  Jen-Yu Wang ,  Cheng-Tung Huang ,  Yu-Ming Lin

IPC: H01L21/28 ,  H01L29/786 ,  H01L29/51 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L27/11585

CPC classification number: H01L29/7869 ,  H01L21/28291 ,  H01L27/11585 ,  H01L29/0649 ,  H01L29/4236 ,  H01L29/4908 ,  H01L29/516 ,  H01L29/66545 ,  H01L29/6684 ,  H01L29/66969

Abstract: An oxide semiconductor transistor includes an oxide semiconductor channel layer, a metal gate, a gate insulation layer, an internal electrode, and a ferroelectric material layer. The metal gate is disposed on the oxide semiconductor channel layer. The gate insulation layer is disposed between the metal gate and the oxide semiconductor channel layer. The internal electrode is disposed between the gate insulation layer and the metal gate. The ferroelectric material layer is disposed between the internal electrode and the metal gate. The ferroelectric material layer in the oxide semiconductor transistor of the present invention is used to enhance the electrical characteristics of the oxide semiconductor transistor.

公开(公告)号：US20170141229A1

公开(公告)日：2017-05-18

申请号：US14960444

申请日：2015-12-07

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L29/78 ,  H01L29/24 ,  H01L29/66 ,  H01L29/165 ,  H01L29/08 ,  H01L29/16 ,  H01L29/161

CPC classification number: H01L29/7847 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02667 ,  H01L21/26526 ,  H01L21/324 ,  H01L29/0847 ,  H01L29/1608 ,  H01L29/161 ,  H01L29/165 ,  H01L29/24 ,  H01L29/32 ,  H01L29/34 ,  H01L29/66636 ,  H01L29/7848

Abstract: The present invention provides a semiconductor device, including a substrate, two gate structures disposed on a channel region of the substrate, an epitaxial layer disposed in the substrate between two gate structures, a first dislocation disposed in the epitaxial layer, wherein the profile of the first dislocation has at least two non-parallel slanting lines, and a second dislocation disposed adjacent to a top surface of the epitaxial layer, and the profile of the second dislocation has at least two non-parallel slanting lines.

公开(公告)号：US09530851B1

公开(公告)日：2016-12-27

申请号：US14841661

申请日：2015-08-31

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： Chia-Lin Lu ,  Chun-Lung Chen ,  En-Chiuan Liou ,  Chih-Wei Yang ,  Yu-Cheng Tung ,  Kun-Yuan Liao ,  Feng-Yi Chang

IPC: H01L29/78 ,  H01L21/8238 ,  H01L29/423 ,  H01L27/088 ,  H01L21/8234

CPC classification number: H01L29/42364 ,  H01L21/823468 ,  H01L21/823475 ,  H01L27/088 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66636 ,  H01L29/7843

Abstract: The present invention provides a semiconductor device, including at least two gate structures, and each gate structure includes a gate, a spacer and a source/drain region, the source/drain region disposed on two sides of the gate. A first dielectric layer is disposed on the substrate and between two gate structures, where the first dielectric layer has a concave surface, and the first dielectric layer directly contacts the spacer. A floating spacer is disposed on the first dielectric layer and on a sidewall of the gate, and at least one contact plug is disposed on the source/drain region, where the contact plug directly contacts the floating spacer.

Abstract translation: 本发明提供一种包括至少两个栅极结构的半导体器件，并且每个栅极结构包括栅极，间隔物和源极/漏极区域，源极/漏极区域设置在栅极的两侧。 第一电介质层设置在衬底上并且在两个栅极结构之间，其中第一电介质层具有凹面，并且第一电介质层直接接触间隔物。 浮动间隔物设置在第一介电层上和栅极的侧壁上，并且至少一个接触插塞设置在源极/漏极区上，其中接触插塞直接接触浮动间隔物。

公开(公告)号：US09525041B2

公开(公告)日：2016-12-20

申请号：US14621358

申请日：2015-02-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/311 ,  H01L29/66 ,  H01L21/033 ,  H01L21/3213

CPC classification number: H01L29/66545 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/32139 ,  H01L29/6653 ,  H01L29/66553

Abstract: A semiconductor process for forming gates with different pitches includes the following steps. A gate layer is formed on a substrate. A first mandrel and a second mandrel are respectively formed on the gate layer. A first spacer material is formed to conformally cover the first mandrel but exposing the second mandrel. A second spacer material is formed to conformally cover the first spacer material and the second mandrel. The first spacer material and the second spacer material are etched to form a first spacer beside the first mandrel and a second spacer beside the second mandrel simultaneously. The first mandrel and the second mandrel are removed. Layouts of the first spacer and the second spacer are transferred to the gate layer, thereby a first gate and a second gate being formed. Moreover, a semiconductor process, which forms the first spacer and the second spacer separately, is also provided.

Abstract translation: 用于形成具有不同间距的门的半导体工艺包括以下步骤。 栅极层形成在基板上。 第一心轴和第二心轴分别形成在栅极层上。 形成第一间隔材料以保形地覆盖第一心轴但暴露第二心轴。 形成第二间隔材料以共形地覆盖第一间隔物材料和第二心轴。 蚀刻第一间隔物材料和第二间隔物材料以在第一心轴旁边形成第一间隔物，同时在第二心轴旁边形成第二间隔物。 去除第一心轴和第二心轴。 第一间隔物和第二间隔物的布置被转移到栅极层，从而形成第一栅极和第二栅极。 此外，还提供了分别形成第一间隔件和第二间隔件的半导体工艺。

公开(公告)号：US20160336187A1

公开(公告)日：2016-11-17

申请号：US14737507

申请日：2015-06-12

Applicant: UNITED MICROELECTRONICS CORP.

Inventor： En-Chiuan Liou ,  Yu-Cheng Tung

IPC: H01L21/308 ,  H01L29/66 ,  H01L21/8234 ,  H01L21/311

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823431

Abstract: A method of forming a semiconductor structure includes following steps. First of all, a plurality of mandrels is formed on a target layer. Next, a plurality of first liner is formed adjacent to two sides of the mandrels. Then, a plurality of second liners is formed adjacent to two sides of the first liners. After these, a plurality of third liners is formed adjacent to two sides of the second liners. Finally, the mandrels and the second liners are simultaneously removed.

Abstract translation: 形成半导体结构的方法包括以下步骤。 首先，在目标层上形成多个心轴。 接下来，与心轴的两侧相邻地形成多个第一衬垫。 然后，与第一衬垫的两侧相邻地形成多个第二衬垫。 之后，与第二衬垫的两侧相邻地形成多个第三衬垫。 最后，心轴和第二衬垫被同时移除。