公开(公告)号：US20080308935A1

公开(公告)日：2008-12-18

申请号：US12141764

申请日：2008-06-18

Applicant: Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

Inventor： Young-Lyong KIM ,  Eun-Chul AHN ,  Jong-Ho LEE ,  Cheul-Joong YOUN ,  Min-Ho O ,  Tae-Sung YOON ,  Cheol-Joon YOO

IPC: H01L23/488 ,  H01L21/56

CPC classification number: H01L21/565 ,  H01L21/566 ,  H01L23/3114 ,  H01L2224/16

Abstract: Provided are a semiconductor chip package, a semiconductor package, and a method of fabricating the same. In some embodiments, the semiconductor chip packages includes a semiconductor chip including an active surface, a rear surface, and side surfaces, bump solder balls provided on bonding pads formed on the active surface, and a molding layer provided to cover the active surface and expose portions of the bump solder balls. The molding layer between adjacent bump solder balls may have a meniscus concave surface, where a height from the active surface to an edge of the meniscus concave surface contacting the bump solder ball is about a 1/7 length of the maximum diameter of a respective bump solder ball at below or above a section of the bump solder ball having the maximum diameter.

Abstract translation: 提供半导体芯片封装，半导体封装及其制造方法。 在一些实施例中，半导体芯片封装包括包括有源表面，后表面和侧表面的半导体芯片，设置在形成在有源表面上的焊盘上的凸块焊球，以及设置成覆盖有源表面并暴露 凸块焊球的一部分。 相邻凸块焊球之间的成型层可以具有弯月面凹面，其中从活性表面到接触凸块焊球的弯液面凹面的边缘的高度约为相应凸块的最大直径的1/7长度 低于或高于具有最大直径的凸块焊球的部分的焊球。

公开(公告)号：US20080296780A1

公开(公告)日：2008-12-04

申请号：US12105117

申请日：2008-04-17

Applicant: Cheol-joon Yoo

Inventor： Cheol-joon Yoo

IPC: H01L23/49 ,  H01B13/18

CPC classification number: H01L25/0657 ,  H01L23/3128 ,  H01L24/05 ,  H01L24/06 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/85 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05556 ,  H01L2224/06135 ,  H01L2224/06136 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/4556 ,  H01L2224/45565 ,  H01L2224/45599 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/4824 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48799 ,  H01L2224/4899 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01007 ,  H01L2924/01012 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01068 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/3862 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/43 ,  H01L2924/01049 ,  H01L2924/01006 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2224/43848 ,  H01L2224/45099

Abstract: Wires included in integrated circuit devices can have separate insulating structures formed thereon. The separate insulating structures on the wires can surround respective cross sectional portions of the wires, which can function as “stand-offs” to prevent immediately neighboring wires (or other neighboring components) from shorting together to thereby allow a reduction in defects associated with devices having reduced pitch between the wires (or other components).

Abstract translation: 集成电路器件中的导线可以在其上形成分离的绝缘结构。 导线上的单独的绝缘结构可以围绕导线的相应截面部分，其可以用作“支架”，以防止立即相邻导线（或其他相邻部件）一起短路，从而允许减少与装置相关的缺陷 在电线（或其他部件）之间具有减小的间距。

公开(公告)号：US20080042253A1

公开(公告)日：2008-02-21

申请号：US11976253

申请日：2007-10-23

Applicant: Cheol-Joon Yoo

Inventor： Cheol-Joon Yoo

IPC: H01L23/488 ,  H01L21/60

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

Abstract: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.

Abstract translation: 堆叠的BGA封装和用于制造堆叠的BGA封装的方法，其具有减小的单元封装的尺寸和/或高度，这也可以减小电连接长度。 堆叠的BGA封装可以包括具有至少一个半导体芯片的基底BGA封装和堆叠在基底BGA封装上的多个BGA封装。 多个焊球可以电连接基底BGA封装和多个BGA封装，然后可以被密封以减少损坏的可能性。

公开(公告)号：US07298033B2

公开(公告)日：2007-11-20

申请号：US10834186

申请日：2004-04-29

Applicant: Cheol-Joon Yoo

Inventor： Cheol-Joon Yoo

IPC: H01L23/12

CPC classification number: H01L25/0657 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73215 ,  H01L2224/73265 ,  H01L2224/8592 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/18165 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/32225

Abstract: A stacked BGA package and a method for manufacturing the stacked BGA package, with reduced size and/or height of a unit package, which may also reduce an electrical connection length. The stacked BGA package may include a base BGA package having at least one semiconductor chip, and a plurality of BGA packages which are stacked on the base BGA package. A plurality of solder balls may electrically connect the base BGA package and the plurality of BGA packages and may then be sealed to reduce the likelihood of damage.

Abstract translation: 堆叠的BGA封装和用于制造堆叠的BGA封装的方法，其具有减小的单元封装的尺寸和/或高度，这也可以减小电连接长度。 堆叠的BGA封装可以包括具有至少一个半导体芯片的基底BGA封装和堆叠在基底BGA封装上的多个BGA封装。 多个焊球可以电连接基底BGA封装和多个BGA封装，然后可以被密封以减少损坏的可能性。

公开(公告)号：US06869264B2

公开(公告)日：2005-03-22

申请号：US10435202

申请日：2003-05-12

Applicant: Cheol-Joon Yoo

Inventor： Cheol-Joon Yoo

IPC: H01L21/50 ,  H01L21/00 ,  H01L21/68 ,  B65B21/02

CPC classification number: H01L21/6835 ,  H01L21/67132 ,  H01L21/6836 ,  H01L2221/68322 ,  H01L2221/68327

Abstract: A method and apparatus for picking up a semiconductor chip, a method and apparatus for removing a semiconductor chip from a dicing tape, and a method of forming a perforated dicing tape are provided. Air may be blown through air holes in a dicing tape to at least partially separate the semiconductor chip from the dicing tape and/or create a space between the semiconductor chip to weaken the adhesion of the dicing tape to the semiconductor chip. The semiconductor chip may then be picked up by a removal member and completely removed from the dicing tape. Semiconductor chips that are not to be removed may be vacuum-suctioned to the dicing tape. UV radiation or heat may be applied to weaken the adhesion of the dicing tape. The semiconductor chip may be detected by an optical detector. Removing the semiconductor chips by air reduces stress and damage to the semiconductor chips.

公开(公告)号：US20110169195A1

公开(公告)日：2011-07-14

申请号：US12962966

申请日：2010-12-08

Applicant: Cheol-joon YOO

Inventor： Cheol-joon YOO

IPC: B29C45/03 ,  B29C45/00

CPC classification number: B29C45/02 ,  B29C45/14655 ,  B29C45/34 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2924/00014

Abstract: Provided are a molding apparatus and a molding method. The molding apparatus a mold including a cavity and a runner. The molding apparatus may further include a pot connected to the runner of the mold, wherein a fluid resin is contained in the pot The molding apparatus may further include a compression gas injection unit configured to inject a compression gas into the pot such that the fluid resin contained in the pot is transferred to the cavity and the runner.

Abstract translation: 提供了一种成型装置和模制方法。 模制装置包括模腔和流道。 成型装置还可以包括连接到模具的流道的罐，其中流体树脂容纳在罐中。成型装置还可以包括压缩气体注入单元，其构造成将压缩气体注入到罐中，使得流体树脂 容纳在锅中的转移到空腔和转轮。

公开(公告)号：US20100013079A1

公开(公告)日：2010-01-21

申请号：US12504209

申请日：2009-07-16

Applicant: In-Sik Cho ,  Yong-Kwan Lee ,  Cheol-Joon Yoo

Inventor： In-Sik Cho ,  Yong-Kwan Lee ,  Cheol-Joon Yoo

IPC: H01L23/28

CPC classification number: H01L21/561 ,  H01L21/565 ,  H01L23/3121 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A package substrate may include an insulating substrate, a circuit pattern and a mold gate pattern. The insulating pattern may have a mold gate region through which a molding member may pass. The circuit pattern may be formed on the insulating substrate. The mold gate pattern may be formed on the mold gate region of the insulating substrate. The mold gate pattern may include a polymer having relatively strong adhesion strength with respect to the insulating substrate and relatively weak adhesion strength with respect to the molding member. Thus, costs of the package substrate and the semiconductor package may be decreased.

Abstract translation: 封装基板可以包括绝缘基板，电路图案和模具浇口图案。 绝缘图案可以具有模制浇口区域，模制构件可以通过该模具浇口区域。 电路图案可以形成在绝缘基板上。 模具栅极图案可以形成在绝缘基板的模具栅极区域上。 模具浇口图案可以包括相对于绝缘基板具有相对较强的粘合强度的聚合物和相对于模制构件的相对弱的粘附强度。 因此，可以降低封装衬底和半导体封装的成本。

公开(公告)号：US20080111284A1

公开(公告)日：2008-05-15

申请号：US11985146

申请日：2007-11-14

Applicant: Cheol-Joon Yoo ,  Tae-Sung Yoon

Inventor： Cheol-Joon Yoo ,  Tae-Sung Yoon

IPC: B29C43/18

CPC classification number: B29C43/183 ,  B29C33/68 ,  B29C43/146 ,  B29C2043/3411 ,  B29C2043/3605 ,  B29K2105/251 ,  B29L2031/772 ,  H05K3/0014

Abstract: In a method of molding a substrate, a molding structure including a release film and flat plate-shaped epoxy molding compound (EMC) is placed on an upper face of a lower die. The substrate is held by a lower face of an upper die facing the lower die. The molding structure and the substrate are compressed using the lower die and the upper die to form a preliminarily molded substrate. The lower die is then downwardly moved from the upper die to form a molded substrate.

Abstract translation: 在成型基板的方法中，将包含脱模膜和平板状环氧树脂模塑料（EMC）的模制结构放置在下模的上表面上。 基板由面向下模的上模的下表面保持。 使用下模和上模压缩成形结构和基板，以形成预成型基板。 然后将下模从上模向下移动以形成模制基板。

公开(公告)号：US07279360B2

公开(公告)日：2007-10-09

申请号：US11536270

申请日：2006-09-28

Applicant: Cheol-Joon Yoo

Inventor： Cheol-Joon Yoo

IPC: H01L21/44

CPC classification number: H01L21/563 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2224/32225 ,  H01L2224/73203 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01079 ,  H01L2924/07811 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/0401

Abstract: Embodiments of the invention provide a semiconductor-chip mounting body, a semiconductor device including the mounting body, and a method of packaging the semiconductor device. According to some embodiments, when a semiconductor chip is mounted on the mounting body as a flip-chip type, an encapsulation process using an encapsulation resin is not required. In some embodiments, the mounting body includes a substrate formed of a polyimide film, a conductive pattern formed of copper, a protection layer pattern formed of PSR, and an adhesive pattern formed on the protection layer pattern. The adhesive pattern can be formed of an insulating material. A plurality of holes, into which a plurality of bumps formed on the semiconductor chip are inserted to be connected to the conductive pattern, are formed in the protection layer pattern and the adhesive pattern.

Abstract translation: 本发明的实施例提供一种半导体芯片安装体，包括该安装体的半导体器件，以及一种封装半导体器件的方法。 根据一些实施例，当半导体芯片作为倒装型安装在安装体上时，不需要使用封装树脂的封装工艺。 在一些实施例中，安装体包括由聚酰亚胺膜形成的基板，由铜形成的导电图案，由PSR形成的保护层图案以及形成在保护层图案上的粘合图案。 粘合剂图案可以由绝缘材料形成。 在保护层图案和粘合剂图案中形成有在半导体芯片上形成的多个凸块插入以连接到导电图案的多个孔。

公开(公告)号：US20050280503A1

公开(公告)日：2005-12-22

申请号：US11147314

申请日：2005-06-08

Applicant: Sang-Woo Lee ,  Cheol-Joon Yoo ,  Dong-Bin Kim

Inventor： Sang-Woo Lee ,  Cheol-Joon Yoo ,  Dong-Bin Kim

IPC: H01L21/02 ,  H01L23/544 ,  H04Q5/22

CPC classification number: H01L23/544 ,  H01L2223/54413 ,  H01L2223/54446 ,  H01L2223/54493 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor wafer, comprising a radio frequency identification (RFID) chip on one side of the semiconductor wafer, on which a pattern has been formed, wherein information on the wafer is input to and/or output from the RFID chip using radio frequency communication.

Abstract translation: 一种半导体晶片，包括在其上形成图案的半导体晶片的一侧上的射频识别（RFID）芯片，其中晶片上的信息被使用射频通信输入到和/或从RFID芯片输出。