公开(公告)号：US20050088895A1

公开(公告)日：2005-04-28

申请号：US10897687

申请日：2004-07-23

Applicant: Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

Inventor： Dirk Manger ,  Till Schloesser ,  Rolf Weis ,  Bernd Goebel ,  Wolfgang Mueller ,  Joachim Nuetzel ,  Klaus Muemmler

IPC: G11C11/34

CPC classification number: H01L27/10841 ,  H01L27/10867

Abstract: Memory cells having a cell capacitor and a cell transistor, which are arranged in a vertical cell structure, are provided in the cell array of a DRAM. By means of a deep implantation or a shallow implantation with subsequent epitaxial growth of silicon, a buried source/drain layer is formed, from which lower source/drain regions of the cell transistors emerge. The upper edge of the buried source/drain layer can be aligned with respect to a lower edge of a gate electrode of the cell transistor, which consequently results in a reduction of a gate/drain capacitance and also a leakage current between the gate electrode and the lower source/drain region. A gate conductor layer structure is applied and there are formed, from the gate conductor layer structure, in a controlled transistor array, gate electrode structures of control transistors and, in the cell array, a body connection structure for the connection of body regions of the cell transistors.

Abstract translation: 在DRAM的单元阵列中设置具有单元电容器和单元晶体管的存储单元，其被布置在垂直单元结构中。 通过深度注入或随后的硅的外延生长的浅注入，形成掩埋源极/漏极层，电池晶体管的下部源极/漏极区域从该衬底源极/漏极层出现。 掩埋源极/漏极层的上边缘可以相对于单元晶体管的栅电极的下边缘对准，这因此导致栅极/漏​​极电容的减小以及栅电极和漏极电极之间的漏电流 较低的源极/漏极区域。 施加栅极导体层结构，并且从栅极导体层结构形成受控晶体管阵列，控制晶体管的栅极电极结构以及在单元阵列中形成用于连接主体区域的主体连接结构 单元晶体管。

公开(公告)号：US07915667B2

公开(公告)日：2011-03-29

申请号：US12137388

申请日：2008-06-11

Applicant: Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

Inventor： Roman Knoefler ,  Michael Specht ,  Franz Hofmann ,  Florian Beug ,  Dirk Manger ,  Stephan Riedel

IPC: H01L29/792 ,  H01L29/788 ,  H01L21/336

CPC classification number: H01L21/28282 ,  H01L21/28273 ,  H01L21/8221 ,  H01L27/11565 ,  H01L27/11568 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792 ,  H01L29/7926

Abstract: In an embodiment, an integrated circuit having a memory cell arrangement is provided. The memory cell arrangement may include a substrate, a fin structure disposed above the substrate, and a memory cell contacting region. The fin structure may include a memory cell region having a plurality of memory cell structures being disposed above one another, each memory cell structure having an active region of a respective memory cell. Furthermore, the memory cell contacting region may be configured to electrically contact each of the memory cell structures, wherein the memory cell contacting region may include a plurality of contact regions, which are at least partially displaced with respect to each other in a direction parallel to the main processing surface of the substrate.

Abstract translation: 在一个实施例中，提供了具有存储单元布置的集成电路。 存储单元布置可以包括基板，设置在基板上方的散热片结构和存储单元接触区域。 鳍结构可以包括具有多个存储单元结构的存储单元区域，每个存储单元结构具有相应存储单元的有源区域。 此外，存储器单元接触区域可以被配置为电接触每个存储单元结构，其中存储单元接触区域可以包括多个接触区域，这些接触区域在平行于存储器单元结构的方向上相对于彼此至少部分地位移 基材的主要加工表面。

公开(公告)号：US07863149B2

公开(公告)日：2011-01-04

申请号：US11223800

申请日：2005-09-09

Applicant: Srivatsa Kundalgurki ,  Peter Moll ,  Dirk Manger ,  Kristin Schupke ,  Till Schloesser

Inventor： Srivatsa Kundalgurki ,  Peter Moll ,  Dirk Manger ,  Kristin Schupke ,  Till Schloesser

IPC: H01L21/20

CPC classification number: H01L28/91 ,  H01L27/10817 ,  H01L27/10852

Abstract: In a method for fabricating a capacitor that includes an electrode structure (80), an auxiliary layer (40) is formed over a substrate (10). A recess (60), which determines the shape of the electrode structure (80), is etched into the auxiliary layer (40), and the electrode structure of the capacitor is formed in the recess. As an example, the auxiliary layer can be a semiconductor layer (40).

Abstract translation: 在制造包括电极结构（80）的电容器的方法中，辅助层（40）形成在衬底（10）上。 确定电极结构（80）的形状的凹部（60）被蚀刻到辅助层（40）中，电容器的电极结构形成在凹部中。 作为示例，辅助层可以是半导体层（40）。

公开(公告)号：US07737049B2

公开(公告)日：2010-06-15

申请号：US11831504

申请日：2007-07-31

Applicant: Dirk Manger ,  Stephan Wege ,  Rolf Weis ,  Christoph Noelscher

Inventor： Dirk Manger ,  Stephan Wege ,  Rolf Weis ,  Christoph Noelscher

IPC: H01R43/00 ,  H01L21/02 ,  H01L21/31

CPC classification number: H01L21/266 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/32137 ,  H01L21/32139

Abstract: In one aspect, a method of forming a structure on a substrate is disclosed. For example, the method includes forming a first mask layer and a second mask layer, modifying a material property in regions of the first and second mask layers, and forming the structure based on the modified regions.

Abstract translation: 一方面，公开了一种在衬底上形成结构的方法。 例如，该方法包括形成第一掩模层和第二掩模层，改变第一和第二掩模层的区域中的材料特性，以及基于改质区域形成结构。

公开(公告)号：US07649779B2

公开(公告)日：2010-01-19

申请号：US11749028

申请日：2007-05-15

Applicant: Eike Ruttkowski ,  Detlev Richter ,  Michael Specht ,  Joseph Willer ,  Dirk Manger ,  Kenny Oisin ,  Steffen Meyer ,  Klaus Knobloch ,  Holger Moeller ,  Doris Keitel Schulz ,  Jan Gutsche ,  Gert Koebernik ,  Christoph Friederich

Inventor： Eike Ruttkowski ,  Detlev Richter ,  Michael Specht ,  Joseph Willer ,  Dirk Manger ,  Kenny Oisin ,  Steffen Meyer ,  Klaus Knobloch ,  Holger Moeller ,  Doris Keitel Schulz ,  Jan Gutsche ,  Gert Koebernik ,  Christoph Friederich

IPC: G11C16/00

CPC classification number: H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

Abstract: Embodiments of the present invention relate generally to integrated circuits, methods for manufacturing an integrated circuit, memory modules, and computing systems.

Abstract translation: 本发明的实施例一般涉及集成电路，用于制造集成电路的方法，存储器模块和计算系统。

公开(公告)号：US20090075462A1

公开(公告)日：2009-03-19

申请号：US11855809

申请日：2007-09-14

Applicant: Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

Inventor： Dirk Manger ,  Rolf Weis ,  Christoph Noelscher

IPC: H01L21/425

CPC classification number: H01L21/31144 ,  H01L21/0337 ,  H01L21/0338 ,  H01L21/32139 ,  H01L21/76816

Abstract: The invention relates to a method of fabricating an integrated circuit, including the steps of providing at least one layer; performing a first implantation step, wherein particles are implanted into the layer under a first direction of incidence; performing a second implantation step, wherein particles are implanted into the layer under a second direction of incidence which is different from the first direction of incidence; performing a removal step, wherein the layer is partially removed depending on the local implant dose generated by the first and the second implantation step.

Abstract translation: 本发明涉及一种制造集成电路的方法，包括提供至少一层的步骤; 执行第一注入步骤，其中在第一入射方向上将颗粒注入所述层中; 执行第二注入步骤，其中在与所述第一入射方向不同的第二入射方向上将颗粒注入所述层中; 执行去除步骤，其中根据由第一和第二植入步骤产生的局部植入剂量部分去除该层。

公开(公告)号：US20080237738A1

公开(公告)日：2008-10-02

申请号：US11728970

申请日：2007-03-27

Applicant: Christoph Andreas Kleint ,  Dirk Manger ,  Nicolas Nagel ,  Andreas Taeuber

Inventor： Christoph Andreas Kleint ,  Dirk Manger ,  Nicolas Nagel ,  Andreas Taeuber

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/0847 ,  H01L21/743 ,  H01L27/115 ,  H01L27/11568 ,  H01L29/66833 ,  H01L29/78 ,  H01L29/7881 ,  H01L29/792

Abstract: The present invention relates generally to integrated circuits, a cell, a cell arrangement, a method for manufacturing an integrated circuit, a method for manufacturing a cell arrangement and a memory module. In an embodiment of the invention, an integrated circuit having a cell is provided. The cell includes a first source/drain region, a second source/drain region, an active region between the first source/drain region and the second source/drain region, a gate insulating region disposed above the active region, a gate region disposed above the gate insulating region, and at least one metal structure below the first source/drain region or the second source/drain region.

Abstract translation: 本发明一般涉及集成电路，单元，单元布置，集成电路的制造方法，单元布置的制造方法和存储器模块。 在本发明的实施例中，提供了具有单元的集成电路。 电池包括第一源极/漏极区域，第二源极/漏极区域，第一源极/漏极区域和第二源极/漏极区域之间的有源区域，设置在有源区域上方的栅极绝缘区域， 栅极绝缘区域以及在第一源极/漏极区域或第二源极/漏极区域下方的至少一个金属结构。

公开(公告)号：US20070215986A1

公开(公告)日：2007-09-20

申请号：US11376645

申请日：2006-03-15

Applicant: Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert

Inventor： Dirk Manger ,  Hocine Boubekeur ,  Martin Verhoeven ,  Nicolas Nagel ,  Thomas Tatry ,  Dirk Caspary ,  Matthias Markert

IPC: H01L23/58 ,  H01L21/467

CPC classification number: H01L21/32139 ,  H01L21/0332 ,  H01L27/105 ,  H01L27/112

Abstract: A hard mask layer stack for patterning a layer to be patterned includes a carbon layer disposed on top of the layer to be patterned, a first layer of a material selected from the group of SiO2 and SiON disposed on top of the carbon layer and a silicon layer disposed on top of the first layer. A method of patterning a layer to be patterned includes providing the above described hard mask layer stack on the layer to be patterned and patterning the silicon hard mask layer in accordance with a pattern to be formed in the layer that has to be patterned.

Abstract translation: 用于图案化待图案化层的硬掩模层叠层包括设置在待图案化层的顶部上的碳层，选自第二层由选自SiO 2和SiON中的SiON的材料 碳层顶部和设置在第一层顶部的硅层。 图案化待图案化层的方法包括在待图案化的层上提供上述硬掩模层堆叠，并根据要在图案层中形成的图案来图案化硅硬掩模层。

公开(公告)号：US20070114616A1

公开(公告)日：2007-05-24

申请号：US11287151

申请日：2005-11-23

Applicant: Dirk Manger ,  Till Schloesser

Inventor： Dirk Manger ,  Till Schloesser

IPC: H01L29/76

CPC classification number: H01L29/4983 ,  H01L21/2815 ,  H01L27/10873 ,  H01L29/6656 ,  H01L29/66659 ,  H01L29/7835

Abstract: A field effect transistor, which is arranged in a semiconductor device, comprises a first and a second doped source/drain region, both regions being arranged within a semiconductor substrate on either side of a gate electrode, and a channel region formed within the substrate between both doped source/drain regions beneath said gate electrode. A gate oxide layer is formed upon the semiconductor substrate. The gate electrode contacts a surface of the gate oxide layer and further comprises at least a first and a second conductive layer, wherein the first and second conductive layers are made of materials having different work functions with respect to each other. The first conductive layer contacts the gate oxide layer within a first portion of the surface, and the second conductive layer contacts the gate oxide layer within a second portion of the surface. The first conductive layer is further conductively connected to the second conductive layer.

Abstract translation: 布置在半导体器件中的场效应晶体管包括第一和第二掺杂源极/漏极区域，两个区域布置在栅电极的任一侧上的半导体衬底内，以及形成在衬底内的沟道区域 在所述栅电极下方的掺杂源/漏区两者。 在半导体衬底上形成栅氧化层。 栅极电极接触栅极氧化物层的表面，并且还包括至少第一和第二导电层，其中第一和第二导电层由相对于彼此具有不同功函数的材料制成。 第一导电层在表面的第一部分内接触栅极氧化物层，并且第二导电层在表面的第二部分内接触栅极氧化物层。 第一导电层进一步导电连接到第二导电层。

公开(公告)号：US20070034927A1

公开(公告)日：2007-02-15

申请号：US11272038

申请日：2005-11-14

Applicant: Harald Seidl ,  Dirk Manger ,  Matthias Goldbach ,  Albert Birner ,  Stefan Slesazeck

Inventor： Harald Seidl ,  Dirk Manger ,  Matthias Goldbach ,  Albert Birner ,  Stefan Slesazeck

IPC: H01L29/94

CPC classification number: H01L27/1087 ,  H01L27/10829 ,  H01L29/945

Abstract: A trench storage capacitor includes a buried plate that is lengthened by a doped silicon layer to right over the collar insulating layer. The conductor layer of the trench storage capacitor is preferably applied to a “buried” collar insulating layer and masked with the aid of a protective layer fabricated by ALD. In an exemplary embodiment, the conductor layer is composed of amorphous silicon, which is used as an HSG layer in a lower trench region.

Abstract translation: 沟槽存储电容器包括一掩埋板，其被掺杂的硅层延伸到芯套绝缘层的正上方。 沟槽存储电容器的导体层优选地应用于“埋入”的轴环绝缘层，并借助于由ALD制成的保护层进行掩模。 在示例性实施例中，导体层由非晶硅组成，其被用作下沟槽区域中的HSG层。