中科微点-全球专利检索

  1. Login
  2. Sign Up

Search Results

90 records (took 0.045 seconds)

    Semiconductor memory device and self-refresh method therefor
    11.
    发明授权
    Semiconductor memory device and self-refresh method therefor 有权
    半导体存储器件及其自刷新方法

    公开(公告)号：US07573772B2

    公开(公告)日：2009-08-11

    申请号：US11612866

    申请日：2006-12-19

    Applicant: Kyung-Woo Nam ,  Ho-Cheol Lee

    Inventor： Kyung-Woo Nam ,  Ho-Cheol Lee

    IPC: G11C7/00

    CPC classification number: G11C11/406 ,  G11C7/1075 ,  G11C11/40603 ,  G11C11/40615 ,  G11C11/40618

    Abstract: A semiconductor memory device and a self-refresh method in which the semiconductor memory device includes a plurality of input/output ports having respective independent operation, a period of self-refresh through one of the plurality of input/output ports being subordinate to a kind of operation through another input/output port. Whereby, a refresh characteristic in a multi-port semiconductor memory device including a dual-port semiconductor memory device may be improved.

    Abstract translation: 一种半导体存储器件和自刷新方法，其中所述半导体存储器件包括具有各自独立操作的多个输入/输出端口，所述多个输入/输出端口中的一个输入/输出端口中的一个从属于一种类型的自刷新周期 的操作通过另一个输入/输出端口。 因此，可以提高包括双端口半导体存储器件的多端口半导体存储器件中的刷新特性。

    Optical pickup device and recording medium used therefor
    13.
    发明授权
    Optical pickup device and recording medium used therefor 失效
    光学拾取装置和用于其的记录介质

    公开(公告)号：US07072254B2

    公开(公告)日：2006-07-04

    申请号：US10217330

    申请日：2002-08-13

    Applicant: Dae-sik Kim ,  Soon-kyo Hong ,  Chul-woo Lee ,  Ho-cheol Lee ,  Kun-ho Cho ,  Jang-hoon Yoo

    Inventor： Dae-sik Kim ,  Soon-kyo Hong ,  Chul-woo Lee ,  Ho-cheol Lee ,  Kun-ho Cho ,  Jang-hoon Yoo

    IPC: G11B5/09 ,  G11B7/24

    CPC classification number: G11B7/13922 ,  G11B7/123 ,  G11B7/1356 ,  G11B7/1374 ,  G11B7/139 ,  G11B7/24056

    Abstract: An optical pickup device includes a light unit for irradiating a light beam having a wavelength longer than 650 nm onto a recording medium and receiving and detecting a light beam reflected by the recording medium, and an objective tens formed of a single lens having an NA of 0.7 or more to form a light spot on the recording medium by condensing an incident light beam emitted from the light unit. A recording medium has a recording density of a DVD family or more and is formed of a material suitable for a long wavelength of 700 nm or more so that a reproduction signal by a reflectance of a recording surface is optimized. Thus, a compact high density optical recording/reproducing apparatus which is inexpensive and has high performance can be realized.

    Abstract translation: 一种光学拾取装置，包括用于将长度大于650nm的波长的光束照射到记录介质上并接收和检测由记录介质反射的光束的光单元，以及由具有NA 0.7以上，通过会聚来自光单元的入射光束，在记录介质上形成光斑。 记录介质具有DVD系列以上的记录密度，并且由适合于700nm以上的长波长的材料形成，使得通过记录面的反射率的再现信号被优化。 因此，可以实现廉价且具有高性能的紧凑型高密度光学记录/再现装置。

    Semiconductor package having multiple embedded chips
    14.
    发明申请
    Semiconductor package having multiple embedded chips 有权
    具有多个嵌入式芯片的半导体封装

    公开(公告)号：US20050001300A1

    公开(公告)日：2005-01-06

    申请号：US10803043

    申请日：2004-03-18

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: H01L23/12 ,  H01L25/065 ,  H01L21/48 ,  H01L23/52

    CPC classification number: H01L25/065 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/49113 ,  H01L2924/00014

    Abstract: A semiconductor package includes multiple embedded chips, each chip including a common circuit having substantially the same common function. The common circuit in a selected one of the chips is enabled. The common circuit in one or more other ones of the chips is disabled. As a result, the enabled common circuit performs the common function for the selected chip and the one or more other chips.

    Abstract translation: 半导体封装包括多个嵌入式芯片，每个芯片包括具有基本上相同的共同功能的公共电路。 所选择的一个芯片中的公共电路被使能。 一个或多个其他芯片中的公共电路被禁用。 结果，使能的公共电路执行所选择的芯片和一个或多个其他芯片的共同功能。

    Synchronous memory devices having dual port capability for graphics and other applications
    15.
    发明授权
    Synchronous memory devices having dual port capability for graphics and other applications 有权
    具有用于图形和其他应用的双端口能力的同步存储器件

    公开(公告)号：US6108244A

    公开(公告)日：2000-08-22

    申请号：US384867

    申请日：1999-08-27

    Applicant: Ho-cheol Lee ,  Kyung-woo Nam

    Inventor： Ho-cheol Lee ,  Kyung-woo Nam

    IPC: G11C11/401 ,  G11C7/10 ,  G11C11/407 ,  G11C11/4096 ,  G11C7/00

    CPC classification number: G11C7/1051 ,  G11C11/4096 ,  G11C7/1072

    Abstract: Graphics memory devices include an output register having an input electrically coupled to an output signal line (DO) and first and second data output buffers responsive to first and second clock signals (CLK1, CLK2), respectively. The first data output buffer has an input electrically coupled to the output signal line (DO) and the second data output buffer has an input electrically coupled to an output of the output register. These memory devices also include at least one memory cell array and a read data driver that has an input electrically coupled to the memory cell array by an input/output signal line (I/O) and an output electrically coupled to the output signal line (DO). To provide improved performance for graphics processing applications, a clock signal generator is provided that generates the first and second clock signals at different frequencies and/or different phases relative to each other. The second clock signal is preferably generated at a higher frequency than the first clock signal so that data (e.g., screen refresh data) provided by the read data driver to the output register can be serially transmitted from the second data output buffer at a high data rate. This data can also be transmitted in parallel with data being transmitted from the first data output buffer. In particular, the first data output buffer generates data at its output (first port) in response to a rising or falling edge of the first clock signal, but the second data output buffer generates data at its output (second port) in response to rising and falling edges of the second clock signal. Thus, even if the first and second clock signals have the same frequency, the rate of data being transmitted by the second data output buffer can be higher than the rate of data being transmitted by the first data output buffer.

    Abstract translation: 图形存储器件包括分别具有电耦合到输出信号线（DO）的输入和响应于第一和第二时钟信号（CLK1，CLK2）的第一和第二数据输出缓冲器的输出寄存器。 第一数据输出缓冲器具有电耦合到输出信号线（DO）的输入端，而第二数据输出缓冲器具有电耦合到输出寄存器的输出端的输入端。 这些存储器件还包括至少一个存储单元阵列和读数据驱动器，其具有通过输入/输出信号线（I / O）电耦合到存储单元阵列的输入和电耦合到输出信号线的输出 做）。 为了提供用于图形处理应用的改进的性能，提供时钟信号发生器，其产生相对于彼此的不同频率和/或不同相位的第一和第二时钟信号。 优选地，以比第一时钟信号更高的频率生成第二时钟信号，使得由读取数据驱动器向输出寄存器提供的数据（例如，屏幕刷新数据）可以以高数据从第二数据输出缓冲器串行发送 率。 该数据也可以与从第一数据输出缓冲器发送的数据并行发送。 特别地，第一数据输出缓冲器响应于第一时钟信号的上升沿或下降沿在其输出（第一端口）处产生数据，但是第二数据输出缓冲器响应于上升沿而在其输出（第二端口）处产生数据 和第二个时钟信号的下降沿。 因此，即使第一和第二时钟信号具有相同的频率，由第二数据输出缓冲器发送的数据的速率可以高于由第一数据输出缓冲器发送的数据的速率。

    Semiconductor memory device with shared data input/output line
    16.
    发明授权
    Semiconductor memory device with shared data input/output line 失效
    具有共享数据输入/输出线的半导体存储器件

    公开(公告)号：US5886947A

    公开(公告)日：1999-03-23

    申请号：US947280

    申请日：1997-10-08

    Applicant: Ho-Cheol Lee

    Inventor： Ho-Cheol Lee

    IPC: G11C11/417 ,  G11C7/00 ,  G11C7/10 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  G11C11/413 ,  G11C8/00

    CPC classification number: G11C7/22 ,  G11C7/1048

    Abstract: The semiconductor memory device includes a clock signal generating circuit, a precharge circuit, a write circuit, and an input/output circuit. The clock signal generating circuit generates a second clock signal having a second state of a constant interval irrespective of a period of a first clock signal. The precharge circuit precharges a data input/output line in response to a precharge signal. The write circuit transfers, during a write operation, input data signal to the data input/output line each time the second clock signal is a first state under the state that a power signal and the precharge signal are the first state. The input/output circuit transfers data transmitted to the data input/output line to a cell.

    Abstract translation: 半导体存储器件包括时钟信号发生电路，预充电电路，写入电路和输入/输出电路。 时钟信号发生电路产生具有恒定间隔的第二状态的第二时钟信号，而与第一时钟信号的周期无关。 预充电电路响应于预充电信号对数据输入/输出线进行预充电。 在电源信号和预充电信号为第一状态的状态下，每当第二时钟信号为第一状态时，写入电路在写入操作期间将输入数据信号传送到数据输入/输出线。 输入/输出电路将发送到数据输入/输出线的数据传送到一个单元。

    Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines
    17.
    发明授权
    Semiconductor memory device having high speed parallel transmission line operation and a method for forming parallel transmission lines 失效
    具有高速并行传输线操作的半导体存储器件和用于形成并行传输线的方法

    公开(公告)号：US5663913A

    公开(公告)日：1997-09-02

    申请号：US638373

    申请日：1996-04-26

    Applicant: Ho-Cheol Lee ,  Hyun-Soon Jang

    Inventor： Ho-Cheol Lee ,  Hyun-Soon Jang

    IPC: G11C11/41 ,  G11C7/22 ,  G11C11/407 ,  G11C11/409 ,  H01L21/8242 ,  H01L27/108 ,  G11C7/00

    CPC classification number: G11C7/22

    Abstract: A semiconductor memory device has the skew between the individual transmission lines of a parallel transmission bus minimized by the addition of respective load transmission lines to each of the individual transmission lines in the parallel bus. A first circuit unit including a first parallel bank of internal circuits for generating internal control signals is formed adjacent to a predetermined region within a chip. A second circuit unit includes a second parallel bank of internal circuits for performing a predetermined operation in response to an output of the first circuit unit. The second circuit transmits signals to the first circuit over a parallel bus comprised of a plurality of transmission lines connected respectively between the individual internal circuits of the first and second circuit units. A plurality of load transmission lines are connected respectively to predetermined portions of the individual transmission lines to thereby equalize the loads of the transmission lines.

    Abstract translation: 半导体存储器件通过向并行总线中的各个传输线路中的各个传输线路添加相应的负载传输线而使并行传输总线的各个传输线之间的偏移最小化。 在芯片内与预定区域相邻地形成包括用于产生内部控制信号的第一并联的内部电路组的第一电路单元。 第二电路单元包括用于响应于第一电路单元的输出执行预定操作的第二并联的内部电路组。 第二电路通过由分别连接在第一和第二电路单元的各个内部电路之间的多条传输线组成的并行总线向第一电路发送信号。 多个负载传输线分别连接到各个传输线的预定部分，从而均衡传输线的负载。

    Semiconductor memory having a plurality of I/O buses
    18.
    发明授权
    Semiconductor memory having a plurality of I/O buses 失效
    具有多个I / O总线的半导体存储器

    公开(公告)号：US5590086A

    公开(公告)日：1996-12-31

    申请号：US580481

    申请日：1995-12-29

    Applicant: Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    Inventor： Churoo Park ,  Hyun-Soon Jang ,  Chull-Soo Kim ,  Myung-Ho Kim ,  Seung-Hun Lee ,  Si-Yeol Lee ,  Ho-Cheol Lee ,  Tae-Jin Kim ,  Yun-Ho Choi

    IPC: G11C11/401 ,  G11C7/00 ,  G11C7/10 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/409 ,  G11C8/00

    CPC classification number: G11C7/1018 ,  G11C11/406 ,  G11C11/40618 ,  G11C11/4076 ,  G11C11/408 ,  G11C11/4082 ,  G11C11/4087 ,  G11C7/1045 ,  G11C7/1072 ,  G11C7/222 ,  G11C7/225 ,  G11C2207/2281

    Abstract: A synchronous dynamic random access memory capable of accessing data in a memory cell array therein in synchronism with a system clock from an external system such as a central processing unit (CPU). The synchronous DRAM receives an external clock and includes a plurality of memory banks each including a plurality of memory cells and operable in either an active cycle or a precharge cycle, a circuit for receiving a row address strobe signal and latching a logic level of the row address strobe signal in response to the clock, an address input circuit for receiving an externally generated address selecting one of the memory banks, and a circuit for receiving the latched logic level and the address from the address input circuit and for outputting an activation signal to the memory bank selected by the address and an inactivation signals to unselected memory banks when the latched logic level is a first logic level, so that the selected memory bank responsive to the activation signal operates in the active cycle while the unselected memory banks responsive to the inactivation signals operate in the precharge cycle.

    Abstract translation: 能够与来自诸如中央处理单元（CPU）的外部系统的系统时钟同步地访问其中的存储器单元阵列中的数据的同步动态随机存取存储器。 同步DRAM接收外部时钟并且包括多个存储器组，每个存储器组包括多个存储器单元并且可以在有效周期或预充电周期中操作，用于接收行地址选通信号并锁存该行的逻辑电平的电路 响应于时钟的地址选通信号，用于接收选择存储体之一的外部产生的地址的地址输入电路，以及用于从地址输入电路接收锁存的逻辑电平和地址的电路，并将激活信号输出到 当锁存的逻辑电平为第一逻辑电平时，由地址选择的存储器组和对未选择的存储体的失活信号，使得响应于激活信号的所选择的存储器组在活动周期中工作，而未选定的存储器组响应于 灭活信号在预充电循环中工作。

Patent Agency Ranking