公开(公告)号：US20090023264A1

公开(公告)日：2009-01-22

申请号：US12050649

申请日：2008-03-18

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01L21/02

CPC classification number: H01L28/91

Abstract: A method of making planar-type bottom electrode for semiconductor device is disclosed. A sacrificial layer structure is formed on a substrate. Multiple first trenches are defined in the sacrificial layer structure, wherein those first trenches are arranged in a first direction. The first trenches are filled with insulating material to form an insulating layer in each first trench. Multiple second trenches are defined in the sacrificial layer structure between the insulating layers, and are arranged in a second direction such that the second trenches intersect the first trenches. The second trenches are filled with bottom electrode material to form a bottom electrode layer in each second trench. The insulating layers separate respectively the bottom electrode layers apart from each other. Lastly, removing the sacrificial layer structure defines a receiving space by two adjacent insulating layers and two adjacent bottom electrode layers.

Abstract translation: 公开了制造半导体器件的平面型底电极的方法。 在基板上形成牺牲层结构。 在牺牲层结构中限定多个第一沟槽，其中这些第一沟槽被布置在第一方向上。 第一沟槽用绝缘材料填充，以在每个第一沟槽中形成绝缘层。 多个第二沟槽被限定在绝缘层之间的牺牲层结构中，并且被布置在第二方向上，使得第二沟槽与第一沟槽相交。 第二沟槽填充有底部电极材料，以在每个第二沟槽中形成底部电极层。 绝缘层分别分开彼此分离的底部电极层。 最后，去除牺牲层结构通过两个相邻的绝缘层和两个相邻的底部电极层限定了接收空间。

公开(公告)号：US20080199614A1

公开(公告)日：2008-08-21

申请号：US11790432

申请日：2007-04-25

Applicant: Ming-Yen Li ,  Hsiao-Che Wu

Inventor： Ming-Yen Li ,  Hsiao-Che Wu

IPC: C23C16/00

CPC classification number: C23C16/45544 ,  C23C16/4557 ,  C23C16/45572 ,  C23C16/46 ,  C23C16/463

Abstract: A method for improving atomic layer deposition (ALD) performance and an apparatus thereof are disclosed. The apparatus alternates the process temperature of the different ALD steps rapidly, and the process temperature of each step is determined in accordance with the specific precursor and the substrate surface used. In case a higher process temperature is needed, a plurality of heating units of the apparatus increases and keeps the temperature of the deposited substrate to complete surface reaction. When the lower process temperature is needful for the next ALD step, the heating units are turned off to reduce the temperature of the deposited substrate and a gas flow puffed to the heater and the deposited substrate to assist in temperature cooling.

Abstract translation: 公开了一种改善原子层沉积（ALD）性能的方法及其装置。 该装置可以快速地改变不同ALD步骤的工艺温度，并根据具体的前体和所使用的基材表面确定每个步骤的工艺温度。 在需要更高的工艺温度的情况下，该装置的多个加热单元增加并保持沉积的基板的温度以完成表面反应。 当下一个ALD步骤需要较低的工艺温度时，加热单元被关闭以降低沉积的基板的温度，并将气流膨胀到加热器和沉积的基板以辅助温度冷却。

公开(公告)号：US20080132053A1

公开(公告)日：2008-06-05

申请号：US11566166

申请日：2006-12-01

Applicant: Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

Inventor： Hsiao Che Wu ,  Yu Min Tsai ,  Wen Li Tsai

IPC: H01L21/44

CPC classification number: H01L24/11 ,  H01L21/561 ,  H01L23/3128 ,  H01L23/522 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05008 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05169 ,  H01L2224/0517 ,  H01L2224/05176 ,  H01L2224/05178 ,  H01L2224/05181 ,  H01L2224/05184 ,  H01L2224/05186 ,  H01L2224/05548 ,  H01L2224/05569 ,  H01L2224/05624 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05666 ,  H01L2224/05669 ,  H01L2224/0567 ,  H01L2224/05676 ,  H01L2224/05678 ,  H01L2224/05681 ,  H01L2224/05684 ,  H01L2224/05686 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/0001 ,  H01L2924/01005 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01023 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01038 ,  H01L2924/0104 ,  H01L2924/01044 ,  H01L2924/01047 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01077 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/14 ,  H01L2924/0476 ,  H01L2924/0479 ,  H01L2924/0475 ,  H01L2924/0474 ,  H01L2924/0483 ,  H01L2924/0496 ,  H01L2924/01014 ,  H01L2924/013 ,  H01L2924/00014 ,  H01L2924/048

Abstract: An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.

Abstract translation: 集成电路装置包括基板，包括具有位于基板上的导线的电路结构的堆叠结构，包括位于基板上的至少一个支撑构件和覆盖电路结构和支撑构件的顶板的加强结构以及至少一个 接合垫定位在屋顶上并电连接到导电线。 一种集成电路器件的制造方法，其特征在于，在基板上形成具有导线的电路结构的堆叠结构，形成包括所述基板上的至少一个支撑部件的加强结构以及覆盖所述支撑部件和所述电路结构的屋顶， 至少一个焊盘在屋顶上并且电连接到导电线。

公开(公告)号：US20080111212A1

公开(公告)日：2008-05-15

申请号：US11598391

申请日：2006-11-13

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L27/00 ,  H01L21/77

CPC classification number: H01L28/91 ,  H01L27/0805 ,  H01L27/10852

Abstract: A capacitance structure of a semiconductor device and a method for manufacturing the structure are provided. The capacitance structure comprises a plurality of capacitance elements and a plurality of supports. Each of the capacitance elements has a column, and each of the supports is disposed between two adjacent columns by partially connecting onto the outer surface of each of the two adjacent columns. Thereby, the mechanical properties of the capacitance structure can be enhanced.

Abstract translation: 提供半导体器件的电容结构和制造该结构的方法。 电容结构包括多个电容元件和多个支撑件。 每个电容元件具有一列，并且每个支撑件通过部分地连接到两个相邻列中的每一个的外表面上而设置在两个相邻的列之间。 由此，可以提高电容结构的机械特性。

公开(公告)号：US20080102207A1

公开(公告)日：2008-05-01

申请号：US11715619

申请日：2007-03-08

Applicant: Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

Inventor： Yu-Min Tsai ,  Hsiao-Che Wu ,  Wen-Li Tsai

IPC: C23C16/00 ,  F16K21/00

CPC classification number: C23C16/45565 ,  C23C16/45572 ,  C23C16/481 ,  H01L21/67109 ,  H01L21/67115 ,  Y10T137/9464

Abstract: A gas delivering system for an in situ thermal treatment, a thin film deposition and a use of the same are provided. The gas delivering system integrates a thermal treatment system therein so that a thin film deposition and a by rapid thermal annealing can be performed alternatively on a wafer in a reaction chamber. Accordingly, the density of the thin film can be improved and the thermal budget of the process can be reduced.

Abstract translation: 提供了一种用于原位热处理，薄膜沉积及其使用的气体输送系统。 气体输送系统将其中的热处理系统集成在一起，可以在反应室中的晶片上交替地进行薄膜沉积和快速热退火。 因此，可以提高薄膜的密度，并且可以降低该方法的热预算。

公开(公告)号：US07312131B2

公开(公告)日：2007-12-25

申请号：US10998929

申请日：2004-11-30

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L21/20

CPC classification number: H01L29/66181 ,  H01L21/76895 ,  H01L27/10855 ,  H01L27/10867 ,  H01L28/91 ,  H01L29/417 ,  H01L29/945

Abstract: A method of forming a multilayer electrode capacitor is described. A trench is formed in a substrate or in an insulator layer. Two sets of conductive layers are deposited on the inner surface of the trench. The first set of conductive layers is electrically connected to each other, and so is the second set of conductive layers. Each of the second set of conductive layers is inserted between two first conductive layers, and dielectric layers are interposed between two conductive layers to form a multilayer electrode capacitor.

Abstract translation: 描述形成多层电极电容器的方法。 在衬底或绝缘体层中形成沟槽。 两组导电层沉积在沟槽的内表面上。 第一组导电层彼此电连接，第二组导电层也相互电连接。 第二组导电层中的每一个插入在两个第一导电层之间，并且介电层插入在两个导电层之间以形成多层电极电容器。

公开(公告)号：US20070278595A1

公开(公告)日：2007-12-06

申请号：US11309376

申请日：2006-08-02

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L29/78 ,  H01L21/336

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region is provided. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract translation: 提供了一种多鳍场效应晶体管，其包括衬底，氧化物层，导电层，栅极氧化物层和掺杂区域。 衬底被沟槽包围，并且在准备在其上形成栅极的区域中在衬底中形成有至少两个鳍型硅层。 氧化物层设置在沟槽中，氧化物层的上表面比翅片型硅层低。 导电层设置在准备形成栅极的区域中。 导电层的顶表面高于翅片型硅层的表面。 栅氧化层设置在导电层和翅片型硅层之间，并且设置在导电层和衬底之间。 掺杂区域设置在导电层两侧的衬底中。

公开(公告)号：US20100013004A1

公开(公告)日：2010-01-21

申请号：US12174110

申请日：2008-07-16

Applicant: HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

Inventor： HSIAO CHE WU ,  MING YEN LI ,  WEN LI TSAI ,  BIN SIANG TSAI

IPC: H01L29/78

CPC classification number: H01L29/7834 ,  H01L21/28061 ,  H01L29/1037 ,  H01L29/6659 ,  H01L29/66621

Abstract: A recessed channel transistor comprises a semiconductor substrate having a trench isolation structure, a gate structure having a lower block in the semiconductor substrate and an upper block on the semiconductor substrate, two doped regions positioned at two sides of the upper block and above the lower block, and an insulation spacer positioned at a sidewall of the upper block and having a bottom end sandwiched between the upper block and the doped regions. In particular, the two doped regions serves as the source and drain regions, respectively, and the lower block of the gate structure serves as the recessed gate of the recessed channel transistor.

Abstract translation: 凹陷沟道晶体管包括具有沟槽隔离结构的半导体衬底，在半导体衬底中具有下部块的栅极结构和位于半导体衬底上的上部块，位于上部块的两侧和下部块上方的两个掺杂区域 以及位于上块的侧壁处并且具有夹在上块和掺杂区之间的底端的绝缘垫片。 特别地，两个掺杂区域分别用作源极和漏极区，并且栅极结构的下部块用作凹陷沟道晶体管的凹入栅极。

公开(公告)号：US20090127618A1

公开(公告)日：2009-05-21

申请号：US12357410

申请日：2009-01-22

Applicant: Hsiao-Che Wu

Inventor： Hsiao-Che Wu

IPC: H01L29/78

CPC classification number: H01L29/7851 ,  H01L29/66795

Abstract: A multi-fin field effect transistor includes a substrate, an oxide layer, a conductive layer, a gate oxide layer, and a doped region. The substrate is surrounded by a trench, and there are at least two fin-type silicon layers formed in the substrate in a region prepared to form a gate thereon. The oxide layer is disposed in the trench and the top surface of the oxide layer is lower than that of the fin-type silicon layers. The conductive layer is disposed in the region prepared to form a gate. The top surface of the conductive layer is higher than that of the fin-type silicon layers. The gate oxide layer is disposed between the conductive layer and the fin-type silicon layers and disposed between the conductive layer and the substrate. The doped region is disposed in the substrate on both sides of the conductive layer.

Abstract translation: 多鳍场效应晶体管包括衬底，氧化物层，导电层，栅极氧化物层和掺杂区域。 衬底被沟槽包围，并且在准备在其上形成栅极的区域中在衬底中形成有至少两个鳍型硅层。 氧化物层设置在沟槽中，氧化物层的上表面比翅片型硅层低。 导电层设置在准备形成栅极的区域中。 导电层的顶表面高于翅片型硅层的表面。 栅氧化层设置在导电层和翅片型硅层之间，并且设置在导电层和衬底之间。 掺杂区域设置在导电层两侧的衬底中。

公开(公告)号：US20080316674A1

公开(公告)日：2008-12-25

申请号：US12000145

申请日：2007-12-10

Applicant: Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

Inventor： Hsiao-Che Wu ,  Ming-Yen Li ,  Wen-Li Tsai

IPC: H01G4/06 ,  H01G9/00

CPC classification number: H01L28/91 ,  H01G4/252 ,  H01G4/33 ,  H01L27/10852

Abstract: Capacitors and methods for fabricating the same are provided. An exemplary embodiment of a capacitor comprises a dielectric layer and a first conductive layer thereover. A supporting rib is embedded in the first conductive layer and extends along a first direction. A second conductive layer is embedded in the first conductive layer and extends along a second direction perpendicular with the first direction, wherein a portion of the second conductive layer forms across the supporting rib and is structurally supported by the supporting rib. A capacitor layer is formed between the first and second conductive layers to electrically insulate the first and second conductive layers.

Abstract translation: 提供了电容器及其制造方法。 电容器的示例性实施例包括电介质层和其上的第一导电层。 支撑肋嵌入在第一导电层中并且沿着第一方向延伸。 第二导电层被嵌入在第一导电层中并且沿着与第一方向垂直的第二方向延伸，其中第二导电层的一部分跨过支撑肋形成并且在结构上由支撑肋支撑。 在第一和第二导电层之间形成电容器层，以使第一和第二导电层电绝缘。