摘要:
An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front-side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front-side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).
摘要:
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.
摘要:
An integrated circuit device comprises a substrate, a stack structure including circuit structure having conductive lines positioned on the substrate, a reinforcement structure including at least one supporting member positioned on the substrate and a roof covering the circuit structure and the supporting member and at least one bonding pad positioned on the roof and electrically connected to the conductive lines. A method for preparing an integrated circuit device comprises forming a stack structure including circuit structure having conductive lines on a substrate, forming a reinforcement structure including at least one supporting member on the substrate and a roof covering the supporting member and the circuit structure and forming at least one bonding pad on the roof and electrically connecting to the conductive lines.
摘要:
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.
摘要:
An electronic device includes a substrate including a front side, a back side, a thickness between the front side and back side, one or more front-side vias extending from the front side into a part of the thickness, and an interconnect via extending from the back side toward the front side; a contact pad on the front side and including one or more protrusions extending through corresponding front-side vias and into the interconnect via; and an interconnect extending through the interconnect via and into contact with the protrusion(s).
摘要:
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
摘要:
A semiconductor gas sensor is provided that includes a semiconductor body with a passivation layer formed on a surface of thereof. A gas-sensitive control electrode is separated from a channel region by a gap or a control electrode is arranged as a first plate of a capacitor with a gap and a second plate of the capacitor is connected to a gate of the field effect transistor implemented as a Capacitively Controlled Field Effect Transistor. The control electrode has is connected to a reference voltage. A support area is provided with a first support structure and a second support structure. A contact area is provided on the surface of the semiconductor body. A first contact region has a frictional connection and an electrical connection with the control electrode and the second contact region has at least a frictional connection with the control electrode.
摘要:
Embodiments are directed to a method of forming a semiconductor chip package and resulting structures having an annular PSPI region formed under a BLM pad. An annular region is formed under a barrier layer metallurgy (BLM) pad. The annular region includes a photosensitive polyimide (PSPI). A conductive pedestal is formed on a surface of the BLM pad and a solder bump is formed on a surface of the conductive pedestal. The annular PSPI region reduces wafer warpage and ULK peeling stress.
摘要:
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.
摘要:
Technologies are generally described related to three-dimensional integration of integrated circuits (ICs) with spacing for heat dissipation. According to some examples, a self-aligned silicide may be formed in a temporary silicon layer and removed subsequent to bonding of the wafers to achieve improved contact between the combined ICs and enhanced heat dissipation through added spacing between the ICs.