Equal phase two-dimensional array probe
    12.
    发明授权
    Equal phase two-dimensional array probe 有权
    等相二维阵列探头

    公开(公告)号:US08202222B2

    公开(公告)日:2012-06-19

    申请号:US11975091

    申请日:2007-10-16

    IPC分类号: A61B8/00

    摘要: An ultrasonic image scanning system for scanning an organic object includes a 2D array probe constructed with transducer elements in both azimuth and elevation dimension. There is a multiplexer disposed in one dimension to route the transducer elements to system front-end channels, while the other dimension can sum into the first dimension with various element number.

    摘要翻译: 用于扫描有机物体的超声波图像扫描系统包括由方位角和仰角尺寸的换能器元件构成的2D阵列探针。 有一个多路复用器设置在一个维度上以将换能器元件路由到系统前端通道,而另一个尺寸可以与各种元件数量相加到第一维度中。

    METHOD FOR MAKING SEMICONDUCTOR PACKAGE
    13.
    发明申请
    METHOD FOR MAKING SEMICONDUCTOR PACKAGE 有权
    制造半导体封装的方法

    公开(公告)号:US20110193237A1

    公开(公告)日:2011-08-11

    申请号:US13004029

    申请日:2011-01-11

    IPC分类号: H01L23/48 H01L21/56

    摘要: A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented.

    摘要翻译: 一种组装半导体封装的方法包括在封装材料的后模塑固化之后的快速冷却步骤。 快速冷却步骤包括将冷却的压缩空气吹在包装上约两分钟。 快速冷却步骤不需要同时对包装施加任何夹紧压力。 快速冷却步骤将封装材料的温度从低于5分钟的最长时间内将固化温度降低到冷却温度。 通过使用快速冷却,与在环境空气下的夹紧压力下冷却封装相反,防止由于CTE错配引起的封装翘曲。

    SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT
    14.
    发明申请
    SEMICONDUCTOR INTEGRATED CIRCUIT PACKAGE AND METHOD OF PACKAGING SEMICONDUCTOR INTEGRATED CIRCUIT 有权
    半导体集成电路封装及封装半导体集成电路的方法

    公开(公告)号:US20090236713A1

    公开(公告)日:2009-09-24

    申请号:US12403400

    申请日:2009-03-13

    摘要: In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

    摘要翻译: 在封装半导体IC的方法中,将带附接到引线框架阵列的后表面,并且引线框架阵列保持在模具的上模追逐和下模追逐之间,其中 引线框阵列向上。 上下模具分别相对于引线框架阵列形成上腔体和下腔体。 模具化合物分别注入上腔和下穴。 关于引线之间,芯片之间和/或引线和芯片焊盘之间的间隙,注入上腔的模具复合体在注入到下腔内的模具化合物填充间隙之前在间隙上覆盖磁带的部分 ,使得磁带被压下。 在固化模具化合物之后,除去模具和脱胶,填充间隙的模具化合物从后表面向内凹入,这增加了随后的表面贴装工艺中的可焊性,并且降低了引线短路的可能性, 电路。