公开(公告)号：US20110193237A1

公开(公告)日：2011-08-11

申请号：US13004029

申请日：2011-01-11

申请人： Bin Tian ,  Nan Xu ,  Jinzhong Yao

发明人： Bin Tian ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L23/48 ,  H01L21/56

CPC分类号： H01L23/3107 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented.

摘要翻译： 一种组装半导体封装的方法包括在封装材料的后模塑固化之后的快速冷却步骤。 快速冷却步骤包括将冷却的压缩空气吹在包装上约两分钟。 快速冷却步骤不需要同时对包装施加任何夹紧压力。 快速冷却步骤将封装材料的温度从低于5分钟的最长时间内将固化温度降低到冷却温度。 通过使用快速冷却，与在环境空气下的夹紧压力下冷却封装相反，防止由于CTE错配引起的封装翘曲。

公开(公告)号：US08115288B2

公开(公告)日：2012-02-14

申请号：US13021716

申请日：2011-02-05

申请人： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

发明人： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

IPC分类号： H01L21/60 ,  H01L23/495

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

摘要翻译： 用于减少毛刺形成的有害影响的引线框架包括引线框架，其具有引线，其中顶表面的一部分从第一引线移除，并且底表面的一部分从邻近第一引线的第二引线移除以减少 导线之间的间隔，同时减少了由引线框制造的半导体器件的分割期间引起的毛刺形成的不利影响，例如短路等。

公开(公告)号：US08216886B2

公开(公告)日：2012-07-10

申请号：US13004029

申请日：2011-01-11

申请人： Bin Tian ,  Nan Xu ,  Jinzhong Yao

发明人： Bin Tian ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L21/00

CPC分类号： H01L23/3107 ,  H01L21/56 ,  H01L21/6835 ,  H01L23/49541 ,  H01L24/48 ,  H01L24/85 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85001 ,  H01L2924/00014 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： A method for assembling a semiconductor package includes a rapid cooling step after post mold curing of an encapsulation material. The rapid cooling step includes blowing chilled, compressed air over the package for about two minutes. The rapid cooling step does not require any clamping pressure be simultaneously applied to the package. The rapid cooling step reduces a temperature of the encapsulation material from a curing temperature to the cooled temperature within a maximum period of less than five minutes. By using rapid cooling, as opposed to cooling the package under a clamping pressure with ambient air, package warpage due to CTE mismatches is prevented.

摘要翻译： 一种组装半导体封装的方法包括在封装材料的后模塑固化之后的快速冷却步骤。 快速冷却步骤包括将冷却的压缩空气吹在包装上约两分钟。 快速冷却步骤不需要同时对包装施加任何夹紧压力。 快速冷却步骤将封装材料的温度从低于5分钟的最长时间内将固化温度降低到冷却温度。 通过使用快速冷却，与在环境空气下的夹紧压力下冷却封装相反，防止由于CTE错配引起的封装翘曲。

公开(公告)号：US20110248393A1

公开(公告)日：2011-10-13

申请号：US13021716

申请日：2011-02-05

申请人： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

发明人： Yongsheng Lu ,  Bin Tian ,  Nan Xu ,  Jinzhong Yao ,  Shufeng Zhao

IPC分类号： H01L23/495 ,  H01L21/60

CPC分类号： H01L23/3107 ,  H01L23/49548 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/0665 ,  H01L2924/14 ,  H01L2924/15747 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： A lead frame for reducing detrimental effects of burr formation includes a lead frame that has leads where a portion of a top surface is removed from a first lead and a portion of a bottom surface is removed from a second lead adjacent to the first lead to reduce spacing between leads while reducing the detrimental effects of burr formation, such as shorting and the like, caused during singulation of a semiconductor device manufactured with the lead frame.

摘要翻译： 用于减少毛刺形成的有害影响的引线框架包括引线框架，其具有引线，其中顶表面的一部分从第一引线移除，并且底表面的一部分从邻近第一引线的第二引线移除以减少 导线之间的间隔，同时减少了由引线框制造的半导体器件的分割期间引起的毛刺形成的不利影响，例如短路等。

公开(公告)号：US20160056097A1

公开(公告)日：2016-02-25

申请号：US14556225

申请日：2014-11-30

申请人： Zhigang Bai ,  Xingshou Pang ,  Nan Xu ,  Jinzhong Yao

发明人： Zhigang Bai ,  Xingshou Pang ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L23/495 ,  H01L21/52 ,  H01L21/78 ,  H01L21/56 ,  H01L21/311 ,  H01L21/3205 ,  H01L23/31 ,  H01L21/48

CPC分类号： H01L21/78 ,  H01L21/4842 ,  H01L21/52 ,  H01L21/561 ,  H01L23/3107 ,  H01L23/49551 ,  H01L23/49582 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2924/00014

摘要： A Quad Flat Non-leaded (QFN) semiconductor die package has a semiconductor die mounted on a die flag of a lead frame. A covers the semiconductor die. The housing has a base and sides. There are electrically conductive mounting feet, each of which has an exposed base portion in the base of the housing and an exposed side portion in the one of the sides of the housing. Bond wires electrically connect electrodes of the semiconductor die to respective ones of the mounting feet.

摘要翻译： 四边形扁平无引线（QFN）半导体管芯封装具有安装在引线框架的管芯标记上的半导体管芯。 A覆盖半导体管芯。 房屋有一个基地和两侧。 存在导电安装脚，每个脚在壳体的基部中具有暴露的基部，并且在壳体的一侧中的暴露的侧部。 接合线将半导体管芯的电极与相应的安装脚电连接。

公开(公告)号：US08859336B2

公开(公告)日：2014-10-14

申请号：US13398816

申请日：2012-02-16

申请人： Junhua Luo ,  Zhigang Bai ,  Nan Xu ,  Jinzhong Yao

发明人： Junhua Luo ,  Zhigang Bai ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L21/50 ,  H01L23/433 ,  H01L23/31 ,  H01L23/16 ,  H01L23/00 ,  H01L23/552 ,  H01L21/56

CPC分类号： H01L21/568 ,  H01L21/561 ,  H01L21/565 ,  H01L23/16 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/552 ,  H01L24/97 ,  H01L2224/32245 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/3025 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of assembling semiconductor devices includes placing an array of semiconductor dies on a die support. A cap array structure is provided that has a corresponding array of caps supported by a cap frame structure. The cap array structure and the array of semiconductor dies on the die support are aligned, with the caps extending over corresponding semiconductor dies, in a mold chase. The array of semiconductor dies and the array of caps are encapsulated with a molding compound in the mold chase. The encapsulated units of the semiconductor dies with the corresponding caps are removed from the mold chase and singulated. Singulating the encapsulated units may include removing the cap frame structure from the encapsulated units.

摘要翻译： 一种组装半导体器件的方法包括将半导体管芯的阵列放置在管芯支撑件上。 提供一种帽阵列结构，其具有由帽框架结构支撑的相应的帽阵列。 在模具追逐中，盖阵列结构和模具支撑件上的半导体管芯阵列与盖延伸在对应的半导体管芯上对齐。 半导体管芯阵列和盖阵列通过模具化合物封装在模具追逐中。 将具有相应盖的半导体管芯的封装单元从模具中取出并分离。 编码封装的单元可以包括从封装单元去除盖框架结构。

公开(公告)号：US20140284806A1

公开(公告)日：2014-09-25

申请号：US14183511

申请日：2014-02-18

申请人： Junhua Luo ,  Nan Xu ,  Jinzhong Yao

发明人： Junhua Luo ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L23/48 ,  H01L25/00

CPC分类号： H01L23/49513 ,  H01L23/49575 ,  H01L24/29 ,  H01L24/32 ,  H01L24/83 ,  H01L2224/2919 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/83447 ,  H01L2224/8349 ,  H01L2224/83851 ,  H01L2224/83855 ,  H01L2924/01322 ,  H01L2924/07802 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/0665

摘要： A semiconductor device has first and semiconductor dies having active faces presenting electrical contact elements and back faces attached to first and second bonding areas side by side on an electrically conductive die support. A layer of electrically insulating material is applied to the first bonding area of the die support. A layer of electrically insulating adhesive bonding material attaches the back face of the first semiconductor die to the first bonding area of the die support through the layer of electrically insulating material. A layer of electrically conductive adhesive bonding material attaches the back face of the second semiconductor die to the second bonding area of the die support.

摘要翻译： 半导体器件具有第一半导体管芯和半导体管芯，所述半导体管芯具有在导电管芯支承件上并排连接到第一和第二接合区域的电接触元件和后表面。 将电绝缘材料层施加到模具支撑件的第一结合区域。 一层电绝缘粘合剂粘合材料通过电绝缘材料层将第一半导体管芯的背面附接到管芯支撑件的第一接合区域。 一层导电粘合剂粘合材料将第二半导体管芯的背面连接到管芯支撑件的第二接合区域。

公开(公告)号：US07727817B2

公开(公告)日：2010-06-01

申请号：US12403400

申请日：2009-03-13

申请人： Xuesong Xu ,  Nan Xu ,  Jinzhong Yao

发明人： Xuesong Xu ,  Nan Xu ,  Jinzhong Yao

IPC分类号： H01L21/44 ,  H01L21/48

CPC分类号： H01L21/561 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3107 ,  H01L24/73 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/00012 ,  H01L2924/00014 ,  H01L2924/00

摘要： In a method of packaging a semiconductor IC, a tape is attached to a back surface of a lead frame array, and the lead frame array is held between an upper mold chase and a lower mold chase of a mold, with the back surface of the lead frame array upward. The upper and lower mold chases form an upper cavity and a lower cavity with respect to the lead frame array respectively. A mold compound is injected into the upper and lower cavities respectively. With respect to clearances between leads, between die pads and/or between the leads and the die pads, the mold compound injected into the upper cavity covers the portion of the tape over the clearances before the mold compound injected into the lower cavity fills the clearances, so that the tape is depressed. After curing the mold compound, removing the mold and de-taping, the mold compound filled in the clearances is recessed inward from the back surface, which increases the solderability in the subsequent surface mount process and decreases the possibility of the occurrence of lead short-circuits.

摘要翻译： 在封装半导体IC的方法中，将带附接到引线框架阵列的后表面，并且引线框架阵列保持在模具的上模追逐和下模追逐之间，其中 引线框阵列向上。 上下模具分别相对于引线框架阵列形成上腔体和下腔体。 模具化合物分别注入上腔和下穴。 关于引线之间，芯片之间和/或引线和芯片焊盘之间的间隙，注入上腔的模具复合体在注入到下腔内的模具化合物填充间隙之前在间隙上覆盖磁带的部分 ，使得磁带被压下。 在固化模具化合物之后，除去模具和脱胶，填充间隙的模具化合物从后表面向内凹入，这增加了随后的表面贴装工艺中的可焊性，并且降低了引线短路的可能性， 电路。

公开(公告)号：US20140206124A1

公开(公告)日：2014-07-24

申请号：US14219011

申请日：2014-03-19

申请人： Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

发明人： Jinzhong Yao ,  Wai Yew Lo ,  Lan Chu Tan ,  Xuesong Xu

IPC分类号： H01L41/25

CPC分类号： H01L41/25 ,  G01L19/0069 ,  G01L19/147 ,  H01L24/97 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/49171 ,  H01L2224/49175 ,  H01L2224/97 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2224/85 ,  H01L2924/00 ,  H01L2924/00012

摘要： A method of packaging a pressure sensor die includes providing a lead frame having a die pad and lead fingers that surround the die pad. A tape is attached to a first side of the lead frame. A pressure sensor die is attached to the die pad on a second side of the lead frame and bond pads of the die are connected to the lead fingers. An encapsulant is dispensed onto the second side of the lead frame and covers the lead fingers and the electrical connections thereto. A gel is dispensed onto a top surface of the die and covers the die bond pads and the electrical connections thereto. A lid is attached to the lead frame and covers the die and the gel, and sides of the lid penetrate the encapsulant.

摘要翻译： 包装压力传感器管芯的方法包括提供引线框架，其具有围绕管芯焊盘的管芯焊盘和引线指。 带子附接到引线框架的第一侧。 压力传感器芯片在引线框架的第二侧附接到芯片焊盘，并且芯片的焊盘被连接到引线指。 将密封剂分配到引线框架的第二侧上并且覆盖引线指及其电连接。 将凝胶分配到模具的顶表面上并覆盖芯片接合焊盘及其电连接。 盖子连接到引线框架并覆盖模具和凝胶，并且盖的侧面穿透密封剂。

公开(公告)号：US08643170B2

公开(公告)日：2014-02-04

申请号：US13442878

申请日：2012-04-10

申请人： Junhua Luo ,  Jinzhong Yao ,  Baoguan Yin

发明人： Junhua Luo ,  Jinzhong Yao ,  Baoguan Yin

IPC分类号： H01L23/34

CPC分类号： H01L21/561 ,  H01L23/13 ,  H01L23/3128 ,  H01L23/4334 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L24/97 ,  H01L2224/291 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/32257 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2224/83 ,  H01L2224/85 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/12042 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/014 ,  H01L2924/00 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

摘要： Semiconductor dies are mounted on a heat sink array frame structure. The heat sink array frame structure and the semiconductor dies are assembled together with an insulating substrate that has a corresponding array of apertures on an adhesive tape. The semiconductor dies are connected electrically with electrical contacts on the insulating substrate. The semiconductor dies, heat sinks and electrical connections to the contacts are encapsulated with a mold compound and then the encapsulated array is de-taped and singulated.

摘要翻译： 半导体管芯安装在散热片阵列框架结构上。 散热器阵列框架结构和半导体管芯与绝缘基板组装在一起，绝缘基板在胶带上具有相应的孔阵列。 半导体管芯与绝缘基板上的电触点电连接。 半导体管芯，散热器和与触点的电气连接用模具化合物封装，然后封装的阵列被去磁和分离。