-
11.发明授权Integrated circuit packaging system with a component in an encapsulant cavity and method of fabrication thereof 有权具有密封腔内的部件的集成电路封装系统及其制造方法公开(公告)号：US08309397B2
公开(公告)日：2012-11-13
申请号：US13235755
申请日：2011-09-19
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/18 , H01L31/0203 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： A method for fabricating an encapsulant cavity integrated circuit package system includes: providing an interposer; forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and the interposer; and attaching a component on the interposer in the encapsulant cavity.
摘要翻译： 一种用于制造密封腔的集成电路封装系统的方法，包括：提供插入器; 形成第一集成电路封装，其具有具有封装腔的反向底部端子和所述插入件; 以及将组件附接到所述密封剂腔中的所述插入件上。
-
公开(公告)号：US07622800B2
公开(公告)日：2009-11-24
申请号：US11760712
申请日：2007-06-08
IPC分类号： H01L23/34
CPC分类号： H01L25/105 , H01L2224/48237 , H01L2224/49109 , H01L2224/73265 , H01L2225/1029 , H01L2225/1058 , H01L2924/01046 , H01L2924/01079 , H01L2924/01322 , H01L2924/10253 , H01L2924/00
摘要： A stackable semiconductor package and method includes providing a first semiconductor package having a first plurality of lower leads and a first plurality of upper leads. A second semiconductor package having a second plurality of lower leads is provided. The second plurality of lower leads is attached to the first plurality of upper leads to form a stack of semiconductor packages.
摘要翻译： 可堆叠的半导体封装和方法包括提供具有第一多个下引线和第一多个上引线的第一半导体封装。 提供具有第二多个下引线的第二半导体封装。 第二多个下引线附接到第一多个上引线以形成半导体封装的堆叠。
-
13.发明申请INTEGRATED CIRCUIT PACKAGE SYSTEM WITH FLEXIBLE SUBSTRATE AND RECESSED PACKAGE 有权集成电路封装系统，具有灵活的基板和封装公开(公告)号：US20090016032A1
公开(公告)日：2009-01-15
申请号：US12136002
申请日：2008-06-09
IPC分类号： H05K1/18
CPC分类号： H01L25/105 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/16 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48227 , H01L2224/73253 , H01L2224/73265 , H01L2225/0651 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2225/1088 , H01L2924/00014 , H01L2924/14 , H01L2924/15311 , H01L2924/1815 , H01L2924/19105 , H01L2924/19107 , H01L2924/30107 , H01L2924/00 , H01L2924/00012 , H01L2224/05599
摘要： An integrated circuit package system includes: providing a flexible circuit substrate having a fold; mounting an integrated circuit or an integrated circuit package over the flexible circuit substrate and connected to the flexible circuit substrate with interconnects; and encapsulating the integrated circuit or integrated circuit package with a recessed encapsulation having a first level and a second level, the second level having the flexible circuit substrate folded thereover.
摘要翻译： 集成电路封装系统包括：提供具有折叠的柔性电路基板; 在柔性电路基板上安装集成电路或集成电路封装，并用互连连接到柔性电路基板; 以及用具有第一电平和第二电平的凹入封装封装所述集成电路或集成电路封装，所述第二电平具有在其上折叠的所述柔性电路基板。
-
公开(公告)号：US20080296759A1
公开(公告)日：2008-12-04
申请号：US11757869
申请日：2007-06-04
CPC分类号： H01L21/6835 , H01L21/561 , H01L21/568 , H01L23/3128 , H01L23/49816 , H01L23/49827 , H01L23/5389 , H01L24/19 , H01L24/82 , H01L24/97 , H01L25/105 , H01L2221/68345 , H01L2224/04105 , H01L2224/12105 , H01L2224/16225 , H01L2224/16227 , H01L2224/16245 , H01L2224/24137 , H01L2224/97 , H01L2225/1023 , H01L2225/1029 , H01L2225/1058 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01047 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/15192 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2224/82 , H01L2924/00
摘要： A semiconductor package comprises a semiconductor component (e.g., a die) and a via at least partially covered by an encapsulant. The encapsulant forms substantially parallel top and bottom surfaces, with at least part of the via being exposed on the top surface. At least one conductive pad is exposed on the bottom surface, and the via can electrically couple the top and bottom surfaces, as well as couple the semiconductor component at the top and bottom surfaces. An additional semiconductor component can be coupled to the top surface with a circuit pattern formed on the top surface and coupled to the via.
摘要翻译： 半导体封装包括半导体部件（例如，管芯）和至少部分被密封剂覆盖的通孔。 密封剂形成基本上平行的顶表面和底表面，其中通孔的至少一部分暴露在顶表面上。 至少一个导电焊盘暴露在底表面上，并且通孔可以电耦合顶表面和底表面，以及在顶表面和底表面处连接半导体部件。 附加的半导体部件可以与形成在顶表面上并耦合到通孔的电路图案耦合到顶表面。
-
公开(公告)号：US20080157402A1
公开(公告)日：2008-07-03
申请号：US11618806
申请日：2006-12-30
IPC分类号： H01L23/28
CPC分类号： H01L23/3128 , H01L21/561 , H01L21/568 , H01L21/6835 , H01L23/3135 , H01L23/49861 , H01L23/5389 , H01L24/24 , H01L24/29 , H01L24/45 , H01L24/48 , H01L24/73 , H01L24/85 , H01L24/96 , H01L24/97 , H01L25/0652 , H01L25/165 , H01L2224/12105 , H01L2224/24137 , H01L2224/32225 , H01L2224/45014 , H01L2224/48091 , H01L2224/48225 , H01L2224/48227 , H01L2224/48247 , H01L2224/73265 , H01L2224/85 , H01L2224/92247 , H01L2224/97 , H01L2924/00014 , H01L2924/01006 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/078 , H01L2924/12041 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2224/83 , H01L2924/00 , H01L2924/00012 , H01L2224/45015 , H01L2924/207
摘要： A dual molded multi-chip package system is provided including forming an embedded integrated circuit package system having a first encapsulation partially covering a first integrated circuit die and a lead connected thereto, mounting a semiconductor device over the first encapsulation and connected to the lead, and forming a second encapsulation over the semiconductor device and the embedded integrated circuit package system.
摘要翻译： 提供了一种双模塑多芯片封装系统，包括形成嵌入式集成电路封装系统，其具有部分覆盖第一集成电路管芯的第一封装和与其连接的引线，将半导体器件安装在第一封装上并连接到引线上，以及 在半导体器件和嵌入式集成电路封装系统上形成第二封装。
-
公开(公告)号：US20080157301A1
公开(公告)日：2008-07-03
申请号：US11619563
申请日：2007-01-03
IPC分类号： H01L23/522 , H01L21/768
CPC分类号： B81B7/0061 , B81B2201/0257 , H01L24/73 , H01L2224/32225 , H01L2224/48091 , H01L2224/48137 , H01L2224/48227 , H01L2224/73265 , H01L2924/01046 , H01L2924/01078 , H01L2924/01079 , H01L2924/14 , H01L2924/1461 , H01L2924/19041 , H04R1/04 , H04R1/2869 , H04R19/005 , H04R31/006 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
摘要： A cavity semiconductor package has a pre-molded leadframe construction. The leadframe is formed by molding around a die pad, and plural terminal lands. The leadframe has a hole for an acoustic port, such that the package can be soldered on a back side of a printed circuit board and have air access to a sensor die in the package from a front side of the printed circuit board via the acoustic port. The leadframe may also have a hollow or concave recess that defines an acoustic cavity in conjunction with the sensor die or printed circuit board.
摘要翻译： 空腔半导体封装具有预成型引线框架结构。 引线框通过在芯片焊盘周围模制而形成，并且多个端子焊盘。 引线框架具有用于声学端口的孔，使得封装可以焊接在印刷电路板的背面上，并且通过声学端口从印刷电路板的正面通过空气进入封装中的传感器裸片 。 引线框架还可以具有与传感器芯片或印刷电路板一起限定声腔的中空或凹入的凹部。
-
17.发明授权公开(公告)号：US07364945B2
公开(公告)日：2008-04-29
申请号：US11306628
申请日：2006-01-04
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49816 , H01L24/48 , H01L24/73 , H01L25/03 , H01L25/0655 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/18 , H01L31/0203 , H01L2224/16225 , H01L2224/32225 , H01L2224/32245 , H01L2224/48091 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/06575 , H01L2225/06582 , H01L2225/1005 , H01L2225/1023 , H01L2225/1058 , H01L2225/1088 , H01L2924/00011 , H01L2924/00014 , H01L2924/01067 , H01L2924/14 , H01L2924/15311 , H01L2924/181 , H01L2924/1815 , H01L2924/19041 , H01L2924/19105 , H01L2924/19107 , H01L2924/00 , H01L2924/00012 , H01L2224/0401 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.
摘要翻译： 一种密封腔集成电路封装系统，包括形成第一集成电路封装，其具有具有封装空腔和插入件的反向底部端子，并将组件附接在封装腔中的插入件上。
-
公开(公告)号：US20070108568A1
公开(公告)日：2007-05-17
申请号：US11382983
申请日：2006-05-12
IPC分类号： H01L23/495 , H01L21/00
CPC分类号： H01L23/49555 , H01L23/3107 , H01L24/48 , H01L24/73 , H01L25/105 , H01L2224/32245 , H01L2224/48091 , H01L2224/48247 , H01L2224/73265 , H01L2225/1029 , H01L2924/00014 , H01L2924/14 , H01L2924/1532 , H01L2924/181 , H01L2924/1815 , H01L2924/00012 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： An integrated circuit package to package stacking system is provided including providing a first integrated circuit package, having a configured leadframe, providing a second integrated circuit package, having the configured leadframe, and forming an integrated circuit package pair by electrically connecting the configured leadframe of the first integrated circuit package to the configured leadframe of the second integrated circuit package.
摘要翻译： 提供集成电路封装到封装堆叠系统，包括提供第一集成电路封装，具有构造的引线框架，提供具有所配置的引线框架的第二集成电路封装，以及通过电连接所配置的引线框，形成集成电路封装对 第一集成电路封装到第二集成电路封装的配置的引线框架。
-
公开(公告)号：US20060220210A1
公开(公告)日：2006-10-05
申请号：US11397027
申请日：2006-03-31
申请人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
发明人： Marcos Karnezos , Il Shim , Byung Han , Kambhampati Ramakrishna , Seng Chow
IPC分类号： H01L23/02
CPC分类号： H01L23/3128 , H01L21/563 , H01L23/3135 , H01L23/49575 , H01L23/49833 , H01L23/552 , H01L24/48 , H01L24/49 , H01L24/73 , H01L25/03 , H01L25/0657 , H01L25/105 , H01L25/16 , H01L25/162 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/32245 , H01L2224/48227 , H01L2224/48247 , H01L2224/48465 , H01L2224/49171 , H01L2224/73204 , H01L2224/73265 , H01L2225/0651 , H01L2225/0652 , H01L2225/06568 , H01L2225/06572 , H01L2225/06586 , H01L2225/1023 , H01L2225/1041 , H01L2225/1058 , H01L2924/00014 , H01L2924/01013 , H01L2924/10162 , H01L2924/14 , H01L2924/1433 , H01L2924/1461 , H01L2924/15311 , H01L2924/16195 , H01L2924/181 , H01L2924/19107 , H01L2924/3025 , H01L2924/00 , H01L2924/00012 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.
-
公开(公告)号：US06531784B1
公开(公告)日：2003-03-11
申请号：US09585915
申请日：2000-06-02
IPC分类号： H01L2348
CPC分类号： H01L24/48 , H01L23/49833 , H01L24/45 , H01L24/49 , H01L25/0657 , H01L2224/05553 , H01L2224/32225 , H01L2224/45124 , H01L2224/45144 , H01L2224/48095 , H01L2224/4813 , H01L2224/48472 , H01L2224/48599 , H01L2224/48699 , H01L2224/4899 , H01L2224/4911 , H01L2224/49171 , H01L2224/73265 , H01L2224/85201 , H01L2224/85205 , H01L2225/0651 , H01L2225/06572 , H01L2225/06586 , H01L2924/00014 , H01L2924/01006 , H01L2924/01013 , H01L2924/01014 , H01L2924/01029 , H01L2924/01031 , H01L2924/01079 , H01L2924/014 , H01L2924/10162 , H01L2924/15311 , H01L2924/181 , H01L2924/351 , H01L2924/00 , H01L2924/00012 , H01L2224/85399 , H01L2224/05599
摘要： A semiconductor package incorporates spacer strips enabling one or more semiconductor dies having central terminal pads to be stacked on top of one another within the package and reliably wire bonded to an associated substrate without shorting of the bonded wires. Each of the spacer strips comprises a flat, elongated strip of an insulative material that mount at edges of a surface of a die such that they straddle the central terminal pads thereon. The die is electrically connected to the substrate by a plurality of fine conductive wires having a first end bonded to one of the central terminal pad on the die, a second end bonded to a terminal pad on the substrate, and an intermediate portion between the first and second ends that passes transversely across the top surface of one of the spacer strips. The spacer strips have spaced pads or grooves on or in their top surfaces that captivate the individual wires and thereby redistribute the wires and prevent them from contacting the die and each other.
摘要翻译： 半导体封装包括间隔条，使得一个或多个具有中心端子焊盘的半导体管芯能够在封装内堆叠在彼此的顶部，并且可靠地引线键合到相关联的衬底而不会使接合的引线短路。 每个间隔条包括平坦的，细长的绝缘材料条，其安装在管芯的表面的边缘处，使得它们跨越其上的中心端子焊盘。 芯片通过多个细导电线电连接到基板上，该细导电线具有与芯片上的一个中心端子焊盘接合的第一端，接合到基板上的端子焊盘的第二端和第一端 并且横向穿过一个间隔条的顶表面的第二端。 间隔条在其顶表面上或其顶表面上具有间隔的垫或凹槽，其吸引各个线，从而重新分布电线并防止它们与管芯和彼此接触。
-
-
-
-
-
-
-
-
-
搜索结果
57 条记录 (耗时 0.023 秒)
