公开(公告)号：US20060220209A1

公开(公告)日：2006-10-05

申请号：US11395529

申请日：2006-03-31

申请人： Marcos Karnezos ,  Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

发明人： Marcos Karnezos ,  Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

IPC分类号： H01L23/02

CPC分类号： H01L25/0657 ,  H01L23/3128 ,  H01L23/552 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/85013 ,  H01L2225/0651 ,  H01L2225/06568 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1052 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19106 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： Stacked package assemblies include first and second stacked packages, each having at least one die affixed to, and electrically interconnected with, a die attach side of the package substrate. One package is inverted in relation to the other; that is, the die attach sides of the package substrates face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the packages is by wire bonds connecting the first and second package substrates. The assembly is encapsulated in such a way that both the second package substrate (one side of the assembly) and a portion of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package, and the second package is a land grid array package. Also, methods for making such stacked packages assemblies include steps of providing a cavity molded LGA package, preferably tested as “good”; applying an adhesive onto the surface of the mold cap of the LGA package; providing a singulated CSP; inverting the CSP and placing the inverted CSP onto the adhesive on the LGA mold cap; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the die attach side of the LGA and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the die attach side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the LGA package was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the LGA substrate.

公开(公告)号：US20060220210A1

公开(公告)日：2006-10-05

申请号：US11397027

申请日：2006-03-31

申请人： Marcos Karnezos ,  Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

发明人： Marcos Karnezos ,  Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

IPC分类号： H01L23/02

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49575 ,  H01L23/49833 ,  H01L23/552 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/162 ,  H01L2224/05553 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/0652 ,  H01L2225/06568 ,  H01L2225/06572 ,  H01L2225/06586 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/01013 ,  H01L2924/10162 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： Semiconductor assemblies include a first package, each having at least one die affixed to, and electrically interconnected with, a die attach side of the first package substrate, and a second substrate having a first side and a second (“land”) side, mounted over the molding of the first package with the first side of the second substrate facing the die attach side of the first package substrate. Accordingly, the die attach sides of the first substrate and the first side of the second substrate face one another, and the “land” sides of the substrates face away from one another. Z-interconnection of the package and the substrate is by wire bonds connecting the first and second substrates. The assembly is encapsulated in such a way that both the land side of the second substrate (one side of the assembly) and a portion of the land side of the first package substrate (on the opposite side of the assembly) are exposed, so that second level interconnection and interconnection with additional components may be made. In some embodiments the first package is a chip scale package. Also, methods for making such stacked packages assemblies include steps of providing singulated CSP; applying an adhesive onto the surface of the molding of the CSP; providing a second substrate having first and second sides; inverting the CSP and placing the inverted CSP onto the first side of the second substrate such that the adhesive contacts the first side of the second substrate; curing the adhesive; performing a plasma clean; wire bonding to form z-interconnection between the first side of the second substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose the first side of the second substrate, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the second substrate and an area of the land side of the CSP substrate located within a marginal area; attaching second level interconnect solder balls to sites on exposed area of the CSP substrate; and (where the second substrate was provided in a strip or array) saw singulating to complete the assembly. In some embodiments one or more additional components are stacked over the land side of the second substrate.

公开(公告)号：US20060220256A1

公开(公告)日：2006-10-05

申请号：US11306628

申请日：2006-01-04

申请人： Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

发明人： Il Shim ,  Byung Han ,  Kambhampati Ramakrishna ,  Seng Chow

IPC分类号： H01L23/52

CPC分类号： H01L23/3128 ,  H01L21/563 ,  H01L23/3135 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/03 ,  H01L25/0655 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L25/18 ,  H01L31/0203 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01067 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/19041 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An encapsulant cavity integrated circuit package system including forming a first integrated circuit package with an inverted bottom terminal having an encapsulant cavity and an interposer, and attaching a component on the interposer in the encapsulant cavity.

摘要翻译： 一种密封腔集成电路封装系统，包括形成第一集成电路封装，其具有具有封装空腔和插入件的反向底部端子，并将组件附接在封装腔中的插入件上。

公开(公告)号：US20050090050A1

公开(公告)日：2005-04-28

申请号：US10986510

申请日：2004-11-10

申请人： Il Shim ,  Kambhampati Ramakrishna ,  Seng Chow ,  Byung Han

发明人： Il Shim ,  Kambhampati Ramakrishna ,  Seng Chow ,  Byung Han

IPC分类号： H01L25/065 ,  H01L25/10 ,  H01L25/16 ,  H01L21/8238

CPC分类号： H01L25/0657 ,  H01L24/73 ,  H01L25/03 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48471 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06572 ,  H01L2225/06582 ,  H01L2225/1005 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2225/1088 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/1815 ,  H01L2924/19105 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/0401

摘要： A stacked semiconductor package includes a substrate and a first semiconductor device on the substrate. An interposer is supported above the first semiconductor device opposite the substrate. The interposer is electrically connected to the substrate. A second semiconductor device is mounted on the interposer.

摘要翻译： 堆叠的半导体封装包括衬底和衬底上的第一半导体器件。 插入器被支撑在与衬底相对的第一半导体器件的上方。 插入器电连接到基板。 第二半导体器件安装在插入器上。

公开(公告)号：US20070190690A1

公开(公告)日：2007-08-16

申请号：US11354806

申请日：2006-02-14

申请人： Seng Chow ,  Il Shim ,  Byung Han

发明人： Seng Chow ,  Il Shim ,  Byung Han

IPC分类号： H01L21/00 ,  H01L23/34

CPC分类号： H01L24/97 ,  H01L21/561 ,  H01L21/566 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L25/0657 ,  H01L25/105 ,  H01L25/16 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2224/97 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2225/1088 ,  H01L2225/1094 ,  H01L2924/00014 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01067 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07811 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025 ,  H01L2224/85 ,  H01L2224/83 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： An integrated circuit package system is provided including providing a substrate having a first surface and second surface; mounting interconnects to the first surface; mounting integrated circuit dies to the first surface; embedding the interconnects and the integrated circuit die within an encapsulant on the substrate and leaving top portions of the interconnects exposed; attaching solder balls to the second surface; and singulating the substrate and the encapsulant into a plurality of integrated circuit packages.

摘要翻译： 提供一种集成电路封装系统，包括提供具有第一表面和第二表面的衬底; 将互连件安装到第一表面; 将集成电路模具安装到第一表面; 将所述互连和所述集成电路管芯嵌入在所述衬底上的密封剂中并且使所述互连的顶部部分暴露; 将焊球附接到第二表面; 以及将所述衬底和所述密封剂分离成多个集成电路封装。

公开(公告)号：US20050194698A1

公开(公告)日：2005-09-08

申请号：US10794109

申请日：2004-03-03

申请人： Il Kwon Shim ,  Virgil Ararao ,  Hyeong Hur ,  Byung Han

发明人： Il Kwon Shim ,  Virgil Ararao ,  Hyeong Hur ,  Byung Han

IPC分类号： H01L23/48

CPC分类号： H01L24/73 ,  H01L24/32 ,  H01L2224/16245 ,  H01L2224/29007 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48237 ,  H01L2224/48247 ,  H01L2224/48465 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/10158 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

摘要： An integrated circuit package is provided with a connective structure having a wire bonding zone and a keep-out zone. An integrated circuit die has an undercut defining an undercut zone, which is overlapped by the keep-out zone. A wire is bonded between the integrated circuit die and the connective structure within the wire bonding zone and outside of the keep-out zone.

摘要翻译： 集成电路封装设置有具有引线接合区和保护区的连接结构。 集成电路管芯具有限定了与保护区重叠的底切区的底切。 集成电路管芯和引线接合区域内的结合结构之间的接合线和保护区外部的接合线。

公开(公告)号：US20070273043A1

公开(公告)日：2007-11-29

申请号：US11839020

申请日：2007-08-15

申请人： Rajendra Pendse ,  Byung Han ,  HunTeak Lee

发明人： Rajendra Pendse ,  Byung Han ,  HunTeak Lee

IPC分类号： H01L23/48 ,  H01L21/60

CPC分类号： H01L23/13 ,  H01L23/49833 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/85 ,  H01L2224/05554 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/4807 ,  H01L2224/48091 ,  H01L2224/48095 ,  H01L2224/48227 ,  H01L2224/48458 ,  H01L2224/48465 ,  H01L2224/48471 ,  H01L2224/48475 ,  H01L2224/48479 ,  H01L2224/4848 ,  H01L2224/48499 ,  H01L2224/48599 ,  H01L2224/48644 ,  H01L2224/48647 ,  H01L2224/48699 ,  H01L2224/48744 ,  H01L2224/48747 ,  H01L2224/48844 ,  H01L2224/48847 ,  H01L2224/49109 ,  H01L2224/49175 ,  H01L2224/49433 ,  H01L2224/73265 ,  H01L2224/85051 ,  H01L2224/85205 ,  H01L2224/85385 ,  H01L2224/85444 ,  H01L2224/85447 ,  H01L2224/85986 ,  H01L2224/92 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/15153 ,  H01L2924/1517 ,  H01L2924/15311 ,  H01L2224/85181 ,  H01L2224/85186 ,  H01L2224/78 ,  H01L2924/00 ,  H01L2224/4554

摘要： A semiconductor package has a semiconductor die disposed on a substrate. A bond wire is connected between a first bonding site on the semiconductor die and a second bonding site on the substrate. The first bonding site is a die bond pad; the second bonding site is a stitch bond. The second bonding site has a bond finger formed on the substrate, a conductive layer in direct physical contact with the bond finger, and a bond stud coupled to the bond wire and in direct physical contact with the conductive layer to conduct an electrical signal from the semiconductor die to the bond finger. The bond finger is made of copper. The conductive layer is made of copper or gold. The bond stud is made of gold and overlies a side portion and top portion of the copper layer.

摘要翻译： 半导体封装具有设置在基板上的半导体管芯。 接合线连接在半导体管芯上的第一接合部位和基板上的第二接合部位之间。 第一个结合位置是一个管芯焊盘; 第二粘结部位是针迹。 第二结合部位具有形成在基板上的粘结指状物，与粘结指状物直接物理接触的导电层和耦合到接合线的接合柱，并与导电层直接物理接触以传导来自 半导体裸片粘到手指上。 键指由铜制成。 导电层由铜或金制成。 接合柱由金制成，并覆盖铜层的侧部和顶部。

公开(公告)号：US08735575B2

公开(公告)日：2014-05-27

申请号：US13195344

申请日：2011-08-01

申请人： Gregory Zipfel ,  Byung Han ,  Robert Mach ,  Wenhau Chu

发明人： Gregory Zipfel ,  Byung Han ,  Robert Mach ,  Wenhau Chu

IPC分类号： C07D265/38

CPC分类号： C07D413/12 ,  C07D265/38

摘要： The present invention encompasses phenoxazine derivatives and methods of use thereof.

摘要翻译： 本发明包括吩恶嗪衍生物及其使用方法。

公开(公告)号：US20120035359A1

公开(公告)日：2012-02-09

申请号：US13195344

申请日：2011-08-01

申请人： Gregory Zipfel ,  Byung Han ,  Robert Mach ,  Wenhau Chu

发明人： Gregory Zipfel ,  Byung Han ,  Robert Mach ,  Wenhau Chu

IPC分类号： C07D265/38

CPC分类号： C07D413/12 ,  C07D265/38

摘要： The present invention encompasses phenoxazine derivatives and methods of use thereof.

摘要翻译： 本发明包括吩恶嗪衍生物及其使用方法。

公开(公告)号：US20080043450A1

公开(公告)日：2008-02-21

申请号：US11877613

申请日：2007-10-23

申请人： Dean Kossives ,  Byung Han

发明人： Dean Kossives ,  Byung Han

IPC分类号： H05K7/00 ,  H05K3/00

CPC分类号： H05K1/16 ,  H01L23/3677 ,  H01L23/645 ,  H01L23/66 ,  H01L25/16 ,  H01L2223/6622 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/3025 ,  H05K1/0237 ,  H05K1/141 ,  H05K1/181 ,  H05K3/3436 ,  H05K2201/0191 ,  H05K2201/10674 ,  Y10T29/49124 ,  Y10T29/49155 ,  H01L2224/05599

摘要： A substrate having a ground plane, a first side, and a second side is provided. A via that electrically connects the first side to the second side is formed. A printed wire is formed on the first side, and a printed wire is formed on the second side. A passive component is formed on the first side. The passive component is formed free of a ground plane. An active component is attached to the first side.

摘要翻译： 提供了具有接地面，第一面和第二面的基板。 形成将第一侧电连接到第二侧的通孔。 印刷线形成在第一侧上，印刷线形成在第二面上。 在第一侧形成无源部件。 无源部件形成为没有接地平面。 活动部件附接到第一侧。