公开(公告)号：US09966832B1

公开(公告)日：2018-05-08

申请号：US15590305

申请日：2017-05-09

Applicant: Linear Technology Corporation

Inventor： Michael T. Engelhardt ,  Leonard Shtargot

IPC: H02M1/15 ,  H02M1/14 ,  H02M3/156 ,  H03K5/134 ,  H03K5/135 ,  H03K5/14 ,  H03K17/16 ,  H02M1/00 ,  H02M1/38

CPC classification number: H02M1/143 ,  H02M3/156 ,  H02M2001/0025 ,  H02M2003/1566 ,  H03K5/134 ,  H03K5/135 ,  H03K5/14

Abstract: A predicted ripple in the feedback voltage of a switching converter is generated, based on the ripple over a certain number of recent switching cycles. The DC portion of the feedback voltage is filtered out. This predicted feedback voltage ripple is then added to a fixed reference voltage to create a compensated reference voltage. The compensated reference voltage is applied to the non-inverting input of an error amplifier, and the feedback voltage (having a DC component and ripple) is applied to the inverting input of the error amplifier. Thus, substantially the same ripple component is applied to both inputs and cancels out. Therefore, the output of the error amplifier is not affected by the ripple in the feedback voltage, and a non-rippling control voltage is generated by the error amplifier. As a result, the gain-bandwidth product of the converter can be increased for faster response to transients.

公开(公告)号：US20180115191A1

公开(公告)日：2018-04-26

申请号：US15723631

申请日：2017-10-03

Applicant: Linear Technology Corporation

Inventor： Heath Stewart ,  Andrew J. Gardner ,  David Stover ,  David Dwelley ,  Jeffrey L. Heath

IPC: H02J13/00 ,  G05B15/02

Abstract: One or more Power Sourcing Equipment (PSE) are coupled to points in a network of interconnected nodes. Each node has a first port and a second port. Assume the first port of a first node is receiving DC power from the PSE. The first node, at its second port, then detects an electrical signature from a first port of an adjacent second node. If the proper electrical signature is presented by the adjacent second node, the powered first node closes a switch to pass power between its first port and second port to power the second node via the first port of the second node. All nodes in the network are then sequentially powered up in this manner. If there is a fault between the first node and the second node, the second node will be powered by another node connected to the second port of the second node.

公开(公告)号：US09897981B2

公开(公告)日：2018-02-20

申请号：US14501517

申请日：2014-09-30

Applicant: Linear Technology Corporation

Inventor： David Dwelley ,  Jeffrey Heath ,  Kirk Su ,  Ryan Huff

IPC: G05B11/01 ,  H02J3/00 ,  H04L12/10

CPC classification number: G05B11/01 ,  H02J3/00 ,  H04L12/10 ,  Y10T307/858

Abstract: In a method performed by a PoE system, a PSE provides data and operating voltage over Ethernet wires to a PD. Before the full PoE voltage is supplied, the PSE generates a low current signal received by the PD. A circuit in the PD, connected across its input terminals, has a characteristic analog response to the PSE signal corresponding to the PD's PoE requirements, such as whether the PD is a Type 1 or Type 2 PD. The circuit may be a certain value capacitor, zener diode, resistor, or other circuit. The PSE may generate a fixed current, fixed voltage, or time varying signal. Upon the PSE sensing the magnitude of the analog signal response at a particular time, the PSE associates the response with the PoE requirements of the PD. The PSE then applies the full PoE voltage in accordance with the PD's PoE requirements.

公开(公告)号：US20180046242A1

公开(公告)日：2018-02-15

申请号：US15728453

申请日：2017-10-09

Applicant: Linear Technology Corporation

Inventor： Brett WARNEKE

IPC: G06F1/32 ,  G06F9/445 ,  H04W52/02 ,  H03L7/18 ,  H04B1/00 ,  G06F1/12 ,  H03L5/02

CPC classification number: G06F1/3243 ,  G06F1/12 ,  G06F1/14 ,  G06F1/3234 ,  G06F1/3237 ,  G06F1/3287 ,  G06F1/3293 ,  G06F9/44505 ,  H03L5/02 ,  H03L7/18 ,  H04B1/0003 ,  H04W52/0203 ,  H04W52/0209 ,  Y02D10/171 ,  Y02D70/00 ,  Y02D70/122 ,  Y02D70/144 ,  Y02D70/22

Abstract: A network device includes a network interface circuit, a microprocessor, a timing circuit, and a microsequencer. The timing circuit is configured to, based on a primary timing signal, generate a time signature and switch the network device from an inactive state to an active state when the time signature satisfies a predetermined threshold length of time for packet transmission. The microsequencer circuit is configured to, in response to the network device being switched to the active state, activate and configure the network interface circuit for the packet transmission, independent of the microprocessor and delays encountered by the microprocessor. The device also reduces energy consumption by using a lower frequency secondary oscillator to maintain timing information when a higher frequency primary oscillator is inactivated.

公开(公告)号：US20180026525A1

公开(公告)日：2018-01-25

申请号：US15653170

申请日：2017-07-18

Applicant: Linear Technology Corporation

Inventor： Andrew J. Gardner

IPC: H03H7/01

CPC classification number: H03H7/427 ,  H02M1/44 ,  H03H1/0007 ,  H03H7/0138 ,  H04L12/10 ,  H04L12/40045 ,  H04L25/0272 ,  H04L25/0298

Abstract: In a communications system that conducts differential data via a pair of wires, AC common mode noise is undesirably coupled to the wires in a noisy environment. A hybrid common mode choke (HCMC) attenuates the AC common mode noise while passing the differential data to a PHY. The HCMC includes a CMC (windings with the same polarity) and a differential mode choke (windings with opposite polarities). The CMC attenuates the AC common mode noise, and the DMC passes the attenuated AC common mode noise to termination circuitry to eliminate it. Also disclosed is a technique for Kelvin sensing the DC voltage at the pair of wires, in a PoDL system, by detecting the voltage on wires that do not carry DC current, so as to provide a more accurate measurement.

公开(公告)号：US20180019666A1

公开(公告)日：2018-01-18

申请号：US15465504

申请日：2017-03-21

Applicant: Linear Technology Corporation

Inventor： Xu Zhang ,  Jian Li ,  San Hwa Chee

IPC: H02M3/07 ,  H02M1/08

CPC classification number: H02M3/07 ,  H02M1/08 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/072

Abstract: A method and system of driving a switched capacitor converter having a plurality of switches. A first driver coupled to a first switch is powered by providing a first reference voltage level VCC to a first supply and a GND reference to a second supply node of the first driver. A second driver coupled to a second switch is powered by providing a unidirectional path between the first supply node of a first driver and the first supply node of the second driver and by keeping OFF the second switch while turning ON the first switch. A third driver coupled to a third switch is powered by providing a unidirectional path between the first supply node of a second driver and the first supply node of the third driver and by keeping OFF the first and third switch while turning ON the second switch.

公开(公告)号：US20180019665A1

公开(公告)日：2018-01-18

申请号：US15465339

申请日：2017-03-21

Applicant: Linear Technology Corporation

Inventor： Xu Zhang ,  Jian Li ,  San Hwa Chee

IPC: H02M3/07

CPC classification number: H02M3/07 ,  H02M1/08 ,  H02M1/36 ,  H02M3/073 ,  H02M2003/072

Abstract: Methods and systems of controlling a switched capacitor converter are provided. Upon determining that a voltage across a flying capacitor is above a first threshold, a first current is drawn from a first terminal of the flying capacitor by a first current source, and a second current is provided to a second terminal of the flying capacitor by a second current source. Upon determining that the voltage across the flying capacitor is below a second threshold, the first current is provided to the first terminal of the flying capacitor by the first current source, and the second current is drawn from the second terminal of the flying capacitor by the second current source. Upon determining that the voltage across the flying capacitor is above the second threshold and below the first threshold from the reference voltage, the first and second current sources are turned OFF.

公开(公告)号：US09866245B2

公开(公告)日：2018-01-09

申请号：US15236365

申请日：2016-08-12

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Michael Thomas Engelhardt

IPC: H03K17/30 ,  H04B1/04

CPC classification number: H04B1/0475 ,  H03H11/53 ,  H04B15/04

Abstract: A method and system of providing an active differential resistor. The active differential resistor includes a diode having a first node and a second node. There is a capacitor coupled in series between the first node of the diode and an input of the active differential resistor. There is a current source coupled across the first node and the second node of the diode and configured to forward bias the diode such that a Johnson-Nyquist noise of the active differential resistor is replaced by a shot noise.

公开(公告)号：US09851772B2

公开(公告)日：2017-12-26

申请号：US14831632

申请日：2015-08-20

Applicant: Linear Technology Corporation

Inventor： David Dwelley ,  Andrew J. Gardner

IPC: G06F13/00 ,  G06F1/00 ,  G06F1/32 ,  G06F1/26 ,  G06F13/42 ,  G06F13/40 ,  H04L12/10 ,  H04L12/40

CPC classification number: G06F1/3206 ,  G06F1/263 ,  G06F1/3287 ,  G06F1/3296 ,  G06F13/4022 ,  G06F13/4282 ,  H04L12/10 ,  H04L12/40045

Abstract: A PoDL system includes a PSE supplying DC power and Ethernet data over a single twisted wire pair to a PD. Prior to coupling the DC voltage source to the wire pair, the PD needs to receive sufficient power to perform a detection and classification routine with the PSE to determine whether the PD is PoDL-compatible. The PSE has a low current, pull-up current source coupled to a first wire in the wire pair via a first inductor. This pull-up current charges a capacitor in the PD to a desired operating voltage, and the operating voltage is used to power a PD logic circuit. The PD logic circuit and a PSE logic circuit then control pull-down transistors to communicate detection and classification data via the first wire. After the handshaking phase, the PSE then applies the DC voltage source across the wire pair to power the PD for normal operation.

公开(公告)号：US20170310306A1

公开(公告)日：2017-10-26

申请号：US15493495

申请日：2017-04-21

Applicant: LINEAR TECHNOLOGY CORPORATION

Inventor： Steven TANGHE ,  Ciaran J. BRENNAN

IPC: H03H11/30 ,  H03K17/689 ,  H02M3/07 ,  H03K19/0175 ,  H01L27/02

CPC classification number: H03H11/30 ,  H01L27/0251 ,  H02M3/07 ,  H03K17/689 ,  H03K19/017509

Abstract: Multiple termination impedance values are provided in a switchable termination circuit so as to accommodate multiple transmission line characteristics. In one example, a termination matching circuit includes first and second nodes, a series interconnection of a first switch and a first impedance coupled between the first and second nodes, and another series interconnection of a second switch and a second impedance coupled between the first and second nodes. First and second control circuits respectively control the first and second switches such that a selectable impedance is provided between the first and second nodes through selective activation of the first and second switch devices by the first and second control circuits. In another example, additional nodes and resistors are provided to provide further termination impedance values.