公开(公告)号：US20130032385A1

公开(公告)日：2013-02-07

申请号：US13197162

申请日：2011-08-03

申请人： Peng Cheng Lin ,  Mario Francisco Velez

发明人： Peng Cheng Lin ,  Mario Francisco Velez

IPC分类号： H05K1/18 ,  H05K3/30

CPC分类号： B81B7/0058 ,  B81B2201/0221 ,  B81B2201/0235 ,  B81B2207/095 ,  B81C2203/0136 ,  B81C2203/0163 ,  G01P1/023 ,  H01G5/16 ,  H01L23/315 ,  H01L23/552 ,  H01L2924/0002 ,  Y10T29/49146 ,  H01L2924/00

摘要： This disclosure provides systems and methods for forming a metal thin film shield over a thin film cap to protect electromechanical systems devices in a cavity beneath. In one aspect, a dual or multi layer thin film structure is used to seal a electromechanical device. For example, a metal thin film shield can be mated over an oxide thin film cap to encapsulate the electromechanical device and prevent degradation due to wafer thinning, dicing and package assembly induced stresses, thereby strengthening the survivability of the electromechanical device in the encapsulated cavity. During redistribution layer processing, a metal thin film shield, such as a copper layer, is formed over the wafer surface, patterned and metalized.

摘要翻译： 本公开提供了用于在薄膜盖上形成金属薄膜屏蔽以保护下面空腔中的机电系统装置的系统和方法。 在一个方面，使用双层或多层薄膜结构来密封机电装置。 例如，金属薄膜屏蔽可以配合在氧化物薄膜帽上以封装机电装置，并防止由于晶片变薄，切割和封装组件引起的应力引起的劣化，从而增强机电装置在封装空腔中的生存性。 在再分配层处理期间，在晶片表面上形成诸如铜层的金属薄膜屏蔽，被图案化和金属化。

公开(公告)号：US20100327433A1

公开(公告)日：2010-12-30

申请号：US12491568

申请日：2009-06-25

申请人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

发明人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

IPC分类号： H01L23/34 ,  H01L23/02 ,  H01L21/00

CPC分类号： H01L23/642 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

摘要翻译： 集成电路封装包括去耦电容器。 集成电路封装还包括封装基板。 去耦电容器至少部分地嵌入在封装衬底中。 集成电路封装还包括安装到封装衬底的管芯。 管芯耦合到去耦电容器。 芯片从去耦电容器接收基本上瞬时的电流。

公开(公告)号：US09270254B2

公开(公告)日：2016-02-23

申请号：US13295978

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim ,  Sanghoon Joo

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim ,  Sanghoon Joo

IPC分类号： H03H9/15 ,  H03H9/46 ,  H03H9/24 ,  H03H9/54 ,  H03H9/02

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

公开(公告)号：US08970516B2

公开(公告)日：2015-03-03

申请号：US13235158

申请日：2011-09-16

申请人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

发明人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

IPC分类号： G06F3/041 ,  G02B26/00 ,  H01L21/56 ,  H01L23/31

CPC分类号： G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

摘要： This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

摘要翻译： 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：US20140035935A1

公开(公告)日：2014-02-06

申请号：US13566925

申请日：2012-08-03

申请人： Ravindra V. Shenoy ,  Kwan-Yu Lai ,  Jon Bradley Lasiter ,  Jonghae Kim ,  Mario Francisco Velez ,  Chi Shun Lo ,  Donald William Kidwell ,  Philip Jason Stephanou ,  Justin Phelps Black ,  Evgeni Petrovich Gousev

发明人： Ravindra V. Shenoy ,  Kwan-Yu Lai ,  Jon Bradley Lasiter ,  Jonghae Kim ,  Mario Francisco Velez ,  Chi Shun Lo ,  Donald William Kidwell ,  Philip Jason Stephanou ,  Justin Phelps Black ,  Evgeni Petrovich Gousev

IPC分类号： H05K7/00 ,  H01F41/00 ,  G06T1/00 ,  H01L21/56 ,  H05K1/00 ,  H05K1/09 ,  H01R43/20 ,  H01L23/29

CPC分类号： H01L23/15 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/49827 ,  H01L23/5389 ,  H01L24/19 ,  H01L24/96 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/24195 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2225/107 ,  H01L2924/12042 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/15311 ,  H01L2924/15788 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19105 ,  Y10T29/4902 ,  Y10T29/49117 ,  H01L2924/00 ,  H01L2924/00012

摘要： This disclosure provides systems, methods and apparatus for glass via bars that can be used in compact three-dimensional packages, including embedded wafer level packages. The glass via bars can provide high density electrical interconnections in a package. In some implementations, the glass via bars can include integrated passive components. Methods of fabricating glass via bars are provided. In some implementations, the methods can include patterning and etching photo-patternable glass substrates. Packaging methods employing glass via bars are also provided.

摘要翻译： 本公开提供了可用于紧凑型三维封装（包括嵌入式晶片级封装）的玻璃通孔条的系统，方法和装置。 玻璃通孔棒可以在封装中提供高密度电连接。 在一些实施方案中，玻璃通孔棒可以包括集成的无源部件。 提供制造玻璃通孔条的方法。 在一些实施方案中，所述方法可以包括图案化和蚀刻可光图案化的玻璃基板。 还提供了采用玻璃通孔条的包装方法。

公开(公告)号：US20120075216A1

公开(公告)日：2012-03-29

申请号：US13235158

申请日：2011-09-16

申请人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

发明人： Justin Phelps Black ,  Ravindra V. Shenoy ,  Evgeni Petrovich Gousev ,  Aristotele Hadjichristos ,  Thomas Andrew Myers ,  Jonghae Kim ,  Mario Francisco Velez ,  Je-Hsiung Jeffrey Lan ,  Chi Shun Lo

IPC分类号： G06F3/041 ,  H01L21/02 ,  H03F3/04 ,  H01L27/06

CPC分类号： G02B26/001 ,  H01L21/565 ,  H01L23/3128 ,  H01L2224/16225 ,  H01L2924/09701 ,  H01L2924/12044 ,  H01L2924/1461 ,  H01L2924/00

摘要： This disclosure provides systems, methods and apparatus for combining devices deposited on a first substrate, with integrated circuits formed on a second substrate such as a semiconducting substrate or a glass substrate. The first substrate may be a glass substrate. The first substrate may include conductive vias. A power combiner circuit may be deposited on a first side of the first substrate. The power combiner circuit may include passive devices deposited on at least the first side of the first substrate. The integrated circuit may include a power amplifier circuit disposed on and configured for electrical connection with the power combiner circuit, to form a power amplification system. The conductive vias may include thermal vias configured for conducting heat from the power amplification system and/or interconnect vias configured for electrical connection between the power amplification system and a conductor on a second side of the first substrate.

摘要翻译： 本公开提供了用于组合沉积在第一衬底上的器件与形成在第二衬底（例如半导体衬底或玻璃衬底）上的集成电路的系统，方法和装置。 第一基板可以是玻璃基板。 第一衬底可以包括导电通孔。 功率组合器电路可以沉积在第一衬底的第一侧上。 功率组合器电路可以包括沉积在第一衬底的至少第一侧上的无源器件。 集成电路可以包括设置在功率合成器电路上并被配置为与功率组合器电路电连接的功率放大器电路，以形成功率放大系统。 导电通孔可以包括被配置为用于传导来自功率放大系统的热的热通孔和/或配置用于功率放大系统和第一衬底的第二侧上的导体之间的电连接的互连通孔。

公开(公告)号：US20110248405A1

公开(公告)日：2011-10-13

申请号：US12757570

申请日：2010-04-09

申请人： Yiming Li ,  Mario Francisco Velez ,  Shiqun Gu

发明人： Yiming Li ,  Mario Francisco Velez ,  Shiqun Gu

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H05K3/002 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/386 ,  H05K2201/0394 ,  H01L2924/00

摘要： A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

摘要翻译： 在沉积金属线和蚀刻通孔之前沉积在基板上的阻挡层使用各向同性蚀刻工艺可以在基板中实现通孔中的通孔的低成本制造。 例如，可以使用玻璃基板的湿式蚀刻来通过玻璃基板进行制造，而不会从玻璃基板上的湿法蚀刻短路金属线上进行底切。 阻挡层防止衬底上的导电层与衬底上的多于一条金属线的接触。 制造过程允许在诸如玻璃基板的基板上堆叠设备并且将设备与通孔连接。