公开(公告)号：US20110248405A1

公开(公告)日：2011-10-13

申请号：US12757570

申请日：2010-04-09

申请人： Yiming Li ,  Mario Francisco Velez ,  Shiqun Gu

发明人： Yiming Li ,  Mario Francisco Velez ,  Shiqun Gu

IPC分类号： H01L23/48 ,  H01L21/768

CPC分类号： H05K3/002 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H05K1/0306 ,  H05K3/386 ,  H05K2201/0394 ,  H01L2924/00

摘要： A block layer deposited on a substrate before deposition of metal lines and etching of a through via enables low cost fabrication of through vias in a substrate using isotropic etching processes. For example, wet etching of a glass substrate may be used to fabricate through glass vias without undercut from the wet etching shorting metal lines on the glass substrate. The block layer prevents contact between a conductive layer lining the through via with more than one metal line on the substrate. The manufacturing process allows stacking of devices on substrates such as glass substrates and connecting the devices with through vias.

摘要翻译： 在沉积金属线和蚀刻通孔之前沉积在基板上的阻挡层使用各向同性蚀刻工艺可以在基板中实现通孔中的通孔的低成本制造。 例如，可以使用玻璃基板的湿式蚀刻来通过玻璃基板进行制造，而不会从玻璃基板上的湿法蚀刻短路金属线上进行底切。 阻挡层防止衬底上的导电层与衬底上的多于一条金属线的接触。 制造过程允许在诸如玻璃基板的基板上堆叠设备并且将设备与通孔连接。

公开(公告)号：US20100327433A1

公开(公告)日：2010-12-30

申请号：US12491568

申请日：2009-06-25

申请人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

发明人： Fifin Sweeney ,  Mario Francisco Velez ,  Yuancheng Christopher Pan ,  Shiqun Gu

IPC分类号： H01L23/34 ,  H01L23/02 ,  H01L21/00

CPC分类号： H01L23/642 ,  H01G4/33 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/50 ,  H01L25/0657 ,  H01L2224/0554 ,  H01L2224/05548 ,  H01L2224/05573 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

摘要： An integrated circuit package includes a decoupling capacitor. The integrated circuit package also includes a packaging substrate. The decoupling capacitor is at least partially embedded in the packaging substrate. The integrated circuit package further includes a die mounted to the packaging substrate. The die is coupled to the decoupling capacitor. The die receiving substantially instantaneous current from the decoupling capacitor.

摘要翻译： 集成电路封装包括去耦电容器。 集成电路封装还包括封装基板。 去耦电容器至少部分地嵌入在封装衬底中。 集成电路封装还包括安装到封装衬底的管芯。 管芯耦合到去耦电容器。 芯片从去耦电容器接收基本上瞬时的电流。

公开(公告)号：US20140028543A1

公开(公告)日：2014-01-30

申请号：US13562168

申请日：2012-07-30

申请人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

发明人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC分类号： H01F5/00 ,  B05D5/12 ,  C25D5/02 ,  G06T1/00 ,  G06F3/01 ,  G06F1/16 ,  B05D3/10

CPC分类号： H01F17/0006 ,  G02B26/001 ,  H01F27/2804 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/00 ,  H01L2924/0002

摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

摘要翻译： 本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。 一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。

公开(公告)号：US07602050B2

公开(公告)日：2009-10-13

申请号：US11399017

申请日：2006-04-05

申请人： Laxminarayan Sharma ,  Mario Francisco Velez

发明人： Laxminarayan Sharma ,  Mario Francisco Velez

IPC分类号： H01L23/48

CPC分类号： H01L23/49531 ,  H01L24/48 ,  H01L24/49 ,  H01L2224/05554 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/49171 ,  H01L2224/49433 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/0105 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/181 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2924/00012

摘要： The disclosure provides integrated circuit packages including a lead frame having multiple I/O pads positioned proximate to the lead frame perimeter around a central ground paddle, an integrated circuit die having electrically conductive die terminals positioned on the central ground paddle, and multiple ground circuit pads positioned on and in electrical connection with the central ground paddle. Electrically conductive I/O circuit pads are arranged about the die between the ground circuit pads and the I/O pads, each I/O circuit pad electrically connected to one of the I/O pads. Electrically conductive bond wires connect one or more of the die terminals to one or more I/O circuit pads or one or more ground circuit pads. In certain embodiments, the disclosure further provides an integrated circuit positioned to engage the integrated circuit die in electrical connection with the die terminals. The disclosure also relates to methods of packaging an integrated circuit to reduce packaging parasitics.

摘要翻译： 本公开提供集成电路封装，其包括具有多个I / O焊盘的引线框架，引线框架围绕中心接地焊盘定位成邻近引线框周边;具有定位在中心接地焊盘上的导电管芯端子的集成电路管芯，以及多个接地电路焊盘 定位在中心接地桨上并与电连接。 导电I / O电路板围绕接地电路板和I / O焊盘之间的管芯布置，每个I / O电路板电连接到I / O焊盘之一。 导电接合线将一个或多个管芯端子连接至一个或多个I / O电路焊盘或一个或多个接地电路焊盘。 在某些实施例中，本公开还提供了一种集成电路，其被定位成与集成电路管芯接合，与芯片端子电连接。 本公开还涉及封装集成电路以减少封装寄生效应的方法。

公开(公告)号：US09099986B2

公开(公告)日：2015-08-04

申请号：US13295970

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

IPC分类号： H01L41/053 ,  H03H9/46 ,  H03H9/24 ,  H03H9/02

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿着Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

公开(公告)号：US20130083044A1

公开(公告)日：2013-04-04

申请号：US13295970

申请日：2011-11-14

申请人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

发明人： Chengjie Zuo ,  Changhan Yun ,  Chi Shun Lo ,  Wesley Nathaniel Allen ,  Mario Francisco Velez ,  Jonghae Kim

IPC分类号： G06F13/14 ,  H01L41/053 ,  H01L41/047

CPC分类号： H03H9/462 ,  H03H9/02228 ,  H03H9/2405 ,  H03H9/2426 ,  H03H2009/02503 ,  H03H2009/241

摘要： Electromechanical systems dilation mode resonator (DMR) structures are disclosed. The DMR includes a first electrode layer, a second electrode layer, and a piezoelectric layer formed of a piezoelectric material. The piezoelectric layer has dimensions including a lateral distance (D), in a plane of an X axis and a Y axis perpendicular to the X axis, and a thickness (T), along a Z axis perpendicular to the X axis and the Y axis. A numerical ratio of the thickness and the lateral distance, T/D, is configured to provide a mode of vibration of the piezoelectric layer with displacement along the Z axis and along the plane of the X axis and the Y axis responsive to a signal provided to one or more of the electrodes. Ladder filter circuits can be constructed with DMRs as series and/or shunt elements, and the resonators can have spiral configurations.

摘要翻译： 公开了机电系统扩张模式谐振器（DMR）结构。 DMR包括第一电极层，第二电极层和由压电材料形成的压电层。 压电体层具有在与X轴正交的X轴和Y轴的平面内的横向距离（D）和与X轴正交的Z轴的厚度（T） 。 厚度和横向距离T / D的数值比被配置为提供压电层的振动模式，其具有沿着Z轴的位移并且沿着X轴和Y轴的平面响应所提供的信号 到一个或多个电极。 梯形滤波器电路可以用DMR构造为串联和/或分流元件，并且谐振器可以具有螺旋配置。

公开(公告)号：US20110210438A1

公开(公告)日：2011-09-01

申请号：US12714918

申请日：2010-03-01

申请人： Fifin Sweeney ,  Milind P. Shah ,  Mario Francisco Velez ,  Damion B. Gastelum

发明人： Fifin Sweeney ,  Milind P. Shah ,  Mario Francisco Velez ,  Damion B. Gastelum

IPC分类号： H01L23/488 ,  H01L21/60 ,  H01L23/36

CPC分类号： H01L23/3677 ,  H01L21/6835 ,  H01L23/49816 ,  H01L23/5389 ,  H01L24/16 ,  H01L24/25 ,  H01L24/48 ,  H01L24/82 ,  H01L25/03 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/2518 ,  H01L2224/48091 ,  H01L2224/82001 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01087 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/19107 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

摘要： In a multi-module integrated circuit package having a package substrate and package contacts, a die is embedded in the package substrate with thermal vias that couple hotspots on the embedded die to some of the package contacts.

摘要翻译： 在具有封装衬底和封装触点的多模块集成电路封装中，裸片被嵌入封装衬底中，其中热通孔将嵌入裸片上的热点耦合到一些封装触点。

公开(公告)号：US20110180926A1

公开(公告)日：2011-07-28

申请号：US12695543

申请日：2010-01-28

申请人： Milind P. Shah ,  Mario Francisco Velez ,  Fifin Sweeney

发明人： Milind P. Shah ,  Mario Francisco Velez ,  Fifin Sweeney

IPC分类号： H01L23/12 ,  H01L21/58

CPC分类号： B81C1/0023 ,  B81B2207/012 ,  B81B2207/098 ,  B81C2203/035 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.

摘要翻译： 集成电路封装包括嵌入在封装衬底中的微机电系统（MEMS）器件。 MEMS器件位于封装在封装衬底中的模具上并被气密密封覆盖。 封装基板中的低应力材料围绕着MEMS器件。 此外，互连可以用作支架以减小MEMS器件上的应力。 在MEMS器件的气密密封和包装基底的支撑表面之间，将MEMS器件嵌入距离包装衬底一段距离（例如30-80微米）。 嵌入MEMS器件导致MEMS器件的较低应力。

公开(公告)号：US09001031B2

公开(公告)日：2015-04-07

申请号：US13562168

申请日：2012-07-30

申请人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

发明人： Chi Shun Lo ,  Je-Hsiung Jeffrey Lan ,  Mario Francisco Velez ,  Robert Paul Mikulka ,  Chengjie Zuo ,  Changhan Hobie Yun ,  Jonghae Kim

IPC分类号： G09G5/00 ,  H01B13/00 ,  H01F17/00 ,  H01F27/28 ,  H01L23/522 ,  H01L49/02 ,  G02B26/00

CPC分类号： H01F17/0006 ,  G02B26/001 ,  H01F27/2804 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/00 ,  H01L2924/0002

摘要： This disclosure provides systems, methods and apparatus for vias in an integrated circuit structure such as a passive device. In one aspect, an integrated passive device includes a first conductive trace and a second conductive trace over the first conductive trace with an interlayer dielectric between a portion of the first conductive trace and the second conductive trace. One or more vias are provided within the interlayer dielectric to provide electrical connection between the first conductive trace and the second conductive trace. A width of the vias is greater than a width of at least one of the conductive traces.

摘要翻译： 本公开提供了诸如无源器件的集成电路结构中的通孔的系统，方法和装置。 一方面，集成无源器件包括在第一导电迹线上的第一导电迹线和第二导电迹线，在第一导电迹线的一部分和第二导电迹线之间具有层间电介质。 在层间电介质中提供一个或多个通孔以提供第一导电迹线和第二导电迹线之间的电连接。 通孔的宽度大于至少一个导电迹线的宽度。

公开(公告)号：US08847375B2

公开(公告)日：2014-09-30

申请号：US12695543

申请日：2010-01-28

申请人： Milind P. Shah ,  Mario Francisco Velez ,  Fifin Sweeney

发明人： Milind P. Shah ,  Mario Francisco Velez ,  Fifin Sweeney

IPC分类号： H01L23/02 ,  B81C1/00

CPC分类号： B81C1/0023 ,  B81B2207/012 ,  B81B2207/098 ,  B81C2203/035 ,  H01L24/73 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73265 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： An integrated circuit package includes a microelectromechanical systems (MEMS) device embedded in a packaging substrate. The MEMS device is located on a die embedded in the packaging substrate and covered by a hermetic seal. Low-stress material in the packaging substrate surrounds the MEMS device. Additionally, interconnects may be used as standoffs to reduce stress on the MEMS device. The MEMS device is embedded a distance into the packaging substrate leaving for example, 30-80 microns, between the hermetic seal of the MEMS device and the support surface of the packaging substrate. Embedding the MEMS device results in lower stress on the MEMS device.

摘要翻译： 集成电路封装包括嵌入在封装衬底中的微机电系统（MEMS）器件。 MEMS器件位于封装在封装衬底中的模具上并被气密密封覆盖。 封装基板中的低应力材料围绕着MEMS器件。 此外，互连可以用作支架以减小MEMS器件上的应力。 在MEMS器件的气密密封和包装基底的支撑表面之间，将MEMS器件嵌入距离包装衬底一段距离（例如30-80微米）。 嵌入MEMS器件导致MEMS器件的较低应力。