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公开(公告)号：US11730000B2
公开(公告)日：2023-08-15
申请号：US17493502
申请日：2021-10-04
发明人： Eli Harari , Wu-Yi Chien
IPC分类号： H10B69/00 , H01L23/528 , H10B41/27 , H10B41/30 , H10B43/00 , H10B43/20 , H10B43/30 , G11C16/04 , C25B11/051 , C25B3/25 , C25B11/075 , B01J37/16 , C01G3/00 , C07C1/12 , C22B15/00 , C30B7/14 , C30B29/02 , C30B29/64
CPC分类号： H10B69/00 , B01J37/16 , C01G3/00 , C07C1/12 , C22B15/00 , C25B3/25 , C25B11/051 , C25B11/075 , C30B7/14 , C30B29/02 , C30B29/64 , G11C16/04 , H01L23/528 , H10B41/27 , H10B41/30 , H10B43/00 , H10B43/20 , H10B43/30 , C07C2523/72
摘要： A memory structure formed above a semiconductor substrate includes two or more modules each formed on top of each other separated by a layer of global interconnect conductors. Each memory module may include a 3-dimensional array of memory transistors organized as NOR array strings. Each 3-dimensional array of memory transistors is provided vertical local word lines as gate electrodes to the memory transistors. These vertical local word lines are connected by the layers of global interconnect conductors below and above the 3-dimensional array of memory transistors to circuitry formed in the semiconductor substrate.
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公开(公告)号：US20230247831A9
公开(公告)日：2023-08-03
申请号：US17382126
申请日：2021-07-21
发明人： Vinod Purayath , Yosuke Nosho , Shohei Kamisaka , Michiru Nakane , Eli Harari
IPC分类号： H01L27/11582 , H01L29/51 , H01L21/28
CPC分类号： H01L27/11582 , H01L29/513 , H01L29/40117 , H01L29/518 , H01L29/517
摘要： A process for building a 3-Dimensional NOR memory array avoids the challenge of etching a conductor material that is aimed at providing local word lines at a fine pitch. The process defines the local word lines between isolation shafts that may be carried out at a lower aspect ratio than would be required for etching the conductor material.
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公开(公告)号：US11580038B2
公开(公告)日：2023-02-14
申请号：US17169212
申请日：2021-02-05
发明人： Robert D. Norman , Eli Harari , Khandker Nazrul Quader , Frank Sai-keung Lee , Richard S. Chernicoff , Youn Cheul Kim , Mehrdad Mofidi
IPC分类号： G06F13/38 , G06F13/16 , G06F13/28 , G06F9/4401 , G06F12/0893 , G06F13/42 , G06F9/54 , H01L25/065 , H01L25/18 , G06F12/10
摘要： A high-capacity system memory may be built from both quasi-volatile (QV) memory circuits, logic circuits, and static random-access memory (SRAM) circuits. Using the SRAM circuits as buffers or cache for the QV memory circuits, the system memory may achieve access latency performance of the SRAM circuits and may be used as code memory. The system memory is also capable of direct memory access (DMA) operations and includes an arithmetic logic unit for performing computational memory tasks. The system memory may include one or more embedded processor. In addition, the system memory may be configured for multi-channel memory accesses by multiple host processors over multiple host ports. The system memory may be provided in the dual-in-line memory module (DIMM) format.
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公开(公告)号：US20230037047A1
公开(公告)日：2023-02-02
申请号：US17938638
申请日：2022-10-06
发明人： Robert D. Norman
IPC分类号： G06F3/06
摘要： Semiconductor memory systems and architectures for shared memory access implements memory-centric structures using a quasi-volatile memory. In one embodiment, a memory processor array includes an array of memory cubes, each memory cube in communication with a processor mini core to form a computational memory. In another embodiment, a memory system includes processing units and one or more mini core-memory module both in communication with a memory management unit. Mini processor cores in each mini core-memory module execute tasks designated to the mini core-memory module by a given processing unit using data stored in the associated quasi-volatile memory circuits of the mini core-memory module.
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公开(公告)号：US20230027837A1
公开(公告)日：2023-01-26
申请号：US17812375
申请日：2022-07-13
IPC分类号： H01L27/1159 , H01L27/11597 , G11C11/22
摘要： Thin-film Ferroelectric field-effect transistor (FeFET) may be organized as 3-dimensional NOR memory string arrays. Each 3-dimensional NOR memory string array includes a row of active stack each including a predetermined number of active strips each provided one on top of another and each being spaced apart from another by an isolation layer. Each active strip may include a shared source layer and a shared drain layer shared by the FeFETs provided along the active strip. Data storage in the active strip is provided by ferroelectric elements that can individually electrically set into one of two polarization states. FeFETs on separate active strips may be configured for read, programming or erase operations in parallel.
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公开(公告)号：US11561911B2
公开(公告)日：2023-01-24
申请号：US17183154
申请日：2021-02-23
摘要： A shared memory provides multi-channel access from multiple computing or host devices. A priority circuit prioritizes the multiple memory requests that are submitted as bids from the multiple host channels, such that those memory access requests that do not give rise to a conflict may proceed in parallel. The shared memory may be multi-ported and a routing circuit routes the prioritized memory access request to the appropriate memory ports where the allowed memory access requests may be carried out.
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公开(公告)号：US20220392529A1
公开(公告)日：2022-12-08
申请号：US17661255
申请日：2022-04-28
发明人： Scott Brad Herner
IPC分类号： G11C16/04 , H01L27/11556 , H01L27/11582 , H01L29/792 , H01L29/786
摘要： A thin-film storage transistor includes a charge storage film provided between a channel region and a gate conductor where the charge storage film includes a tunneling dielectric layer formed adjacent the channel region and a charge trapping layer formed adjacent the tunneling dielectric layer. In some embodiments, the charge trapping layer is a layer including silicon, silicon oxide and silicon nitride materials. In one embodiment, the charge trapping layer is a layer including a mixture of silicon, silicon oxide and silicon nitride materials, where the silicon oxide and silicon nitride may or may not be their respective stoichiometric compounds.
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公开(公告)号：US11515309B2
公开(公告)日：2022-11-29
申请号：US17125477
申请日：2020-12-17
发明人： Vinod Purayath , Jie Zhou , Wu-Yi Henry Chien , Eli Harari
IPC分类号： H01L29/66 , H01L27/105 , H01L29/786 , H01L21/3065
摘要： A process includes (a) providing a semiconductor substrate having a planar surface; (b) forming a plurality of thin-film layers above the planar surface of the semiconductor substrate, one on top of another, including among the thin-film layers first and second isolation layers, wherein a significantly greater concentration of a first dopant specie is provided in the first isolation layer than in the second isolation layer; (c) etching along a direction substantially orthogonal to the planar surface through the thin-films to create a trench having sidewalls that expose the thin-film layers; (d) depositing conformally a semiconductor material on the sidewalls of the trench; (e) annealing the first isolation layer at a predetermined temperature and a predetermined duration such that the first isolation layer act as a source of the first dopant specie which dopes a portion of the semiconductor material adjacent the first isolation layer; and (f) selectively etching the semiconductor material to remove the doped portion of the semiconductor material without removing the remainder of the semiconductor material.
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公开(公告)号：US11508693B2
公开(公告)日：2022-11-22
申请号：US17124194
申请日：2020-12-16
IPC分类号： H01L25/065 , H01L25/18
摘要： A memory device includes a first semiconductor wafer portion including two or more adjacent quasi-volatile memory circuits formed on a common semiconductor substrate where each quasi-volatile memory circuit being isolated from an adjacent quasi-volatile memory circuit by scribe lines; and a second semiconductor wafer portion including at least one memory controller circuit formed on a semiconductor substrate. The memory controller circuit includes logic circuits and interface circuits. The memory controller circuit is interconnected to the two or more adjacent quasi-volatile memory circuits of the first semiconductor wafer portion through interconnect structures and the memory controller circuit operates the two or more quasi-volatile memory circuits as one or more quasi-volatile memories.
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公开(公告)号：US11335693B2
公开(公告)日：2022-05-17
申请号：US17170664
申请日：2021-02-08
发明人： Eli Harari , Raul Adrian Cernea
IPC分类号： G11C7/18 , H01L27/11 , H01L27/11578 , H03K19/20 , H03K19/1776 , G11C16/04 , G11C16/08 , G11C16/24 , H01L29/786
摘要： A NOR string includes a number of individually addressable thin-film storage transistors sharing a bit line, with the individually addressable thin-film transistors further grouped into a predetermined number of segments. In each segment, the thin-film storage transistors of the segment share a source line segment, which is electrically isolated from other source line segments in the other segments within the NOR string. The NOR string may be formed along an active strip of semiconductor layers provided above and parallel a surface of a semiconductor substrate, with each active strip including first and second semiconductor sublayers of a first conductivity and a third semiconductor sublayer of a second conductivity, wherein the shared bit line and each source line segment are formed in the first and second semiconductor sublayers, respectively.
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