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    Image sensors and methods of operating the same
    11.
    发明申请
    Image sensors and methods of operating the same 有权
    图像传感器及其操作方法

    公开(公告)号：US20110108704A1

    公开(公告)日：2011-05-12

    申请号：US12805723

    申请日：2010-08-17

    Applicant: Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    Inventor： Ho-jung Kim ,  U-in Chung ,  Jai-kwang Shin ,  Sun-il Kim ,  I-hun Song ,  Chang-jung Kim ,  Sang-hun Jeon

    IPC: H01L27/146 ,  H01L31/09 ,  H01L31/101 ,  H01L31/102

    CPC classification number: H04N9/045 ,  H01L27/14643 ,  H04N5/3745

    Abstract: Image sensors and methods of operating the same. An image sensor includes a pixel array including a plurality of pixels. Each of the plurality of pixels includes a photo sensor, the voltage-current characteristics of which vary according to energy of incident light, and that generates a sense current determined by the energy of the incident light; a reset unit that is activated to generate a reference current, according to a reset signal for resetting at least one of the plurality of pixels; and a conversion unit that converts the sense current and the reference current into a sense voltage and a reference voltage, respectively.

    Abstract translation: 图像传感器及其操作方法。 图像传感器包括包括多个像素的像素阵列。 多个像素中的每一个包括光电传感器，其电压 - 电流特性根据入射光的能量而变化，并且产生由入射光的能量确定的感测电流; 根据用于复位所述多个像素中的至少一个的复位信号，被激活以产生参考电流的复位单元; 以及转换单元，其将感测电流和参考电流分别转换为感测电压和参考电压。

    Method for fabricating a capacitor in a semiconductor memory device
    12.
    发明授权
    Method for fabricating a capacitor in a semiconductor memory device 失效
    在半导体存储器件中制造电容器的方法

    公开(公告)号：US06391714B2

    公开(公告)日：2002-05-21

    申请号：US09738296

    申请日：2000-12-18

    Applicant: Chul-Ho Shin ,  U In Chung

    Inventor： Chul-Ho Shin ,  U In Chung

    IPC: H01L218242

    CPC classification number: H01L28/84 ,  H01L21/3143 ,  H01L27/10814 ,  H01L27/10855 ,  Y10T29/41

    Abstract: A method for making a capacitor of a semiconductor memory device capable of providing increased capacitance without degraded resolution, as well as without the removal of any interlayer insulation layers upon formation of a lower electrode for the capacitor, wherein after formation of an access transistor on a semiconductor substrate, a first interlayer insulation layer for planarization of a surface of the semiconductor substrate and a second interlayer insulation layer for formation of the capacitor lower electrode are formed. After formation of an opening for exposing a part of an impurity diffusion region of the access transistor by etching a part of the first and second interlayer insulating layers, a spacer is formed within the opening. Further, after deposition of a conductive layer for the capacitor lower electrode onto a surface of the substrate, a planarization process is carried out until a part of the upper surface of the spacer is exposed. Finally, after removal of the exposed spacer, the dielectric layer and a conductive layer for the upper electrode of the capacitor are formed in sequence. The method does not require any additional insulation layer evaporation process, since the interlayer insulation layer for formation of the reverse storage electrode could be used for formation of a gate contact of a logic region, without removal. Consequently, simplification of fabrication process for a capacitor is achieved.

    Abstract translation: 一种用于制造半导体存储器件的电容器的方法，其能够提供增加的电容而不降低分辨率，以及在形成用于电容器的下电极时不去除任何层间绝缘层，其中在形成存取晶体管 半导体衬底，用于使半导体衬底的表面平坦化的第一层间绝缘层和用于形成电容器下电极的第二层间绝缘层。 在形成用于通过蚀刻第一和第二层间绝缘层的一部分来暴露存取晶体管的一部分杂质扩散区的开口，在开口内形成间隔物。 此外，在将电容器下电极的导电层沉积到基板的表面上之后，进行平坦化处理直到间隔件的上表面的一部分露出。 最后，在去除暴露的间隔物之后，依次形成电介质层和用于电容器的上电极的导电层。 该方法不需要任何额外的绝缘层蒸发工艺，因为用于形成反向存储电极的层间绝缘层可用于形成逻辑区域的栅极接触而不去除。 因此，实现了电容器制造工艺的简化。

    METHODS OF FABRICATING VERTICAL CHANNEL FIELD EFFECT TRANSISTORS HAVING INSULATING LAYERS THEREON
    14.
    发明申请
    METHODS OF FABRICATING VERTICAL CHANNEL FIELD EFFECT TRANSISTORS HAVING INSULATING LAYERS THEREON 有权
    制造具有绝缘层的垂直通道场效应晶体管的方法

    公开(公告)号：US20070066018A1

    公开(公告)日：2007-03-22

    申请号：US11556804

    申请日：2006-11-06

    Applicant: Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    Inventor： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC: H01L21/336

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

    Abstract translation: 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。

    Wire forming method for semiconductor device
    15.
    发明授权
    Wire forming method for semiconductor device 失效
    半导体器件的成线方法

    公开(公告)号：US5604156A

    公开(公告)日：1997-02-18

    申请号：US560913

    申请日：1995-11-20

    Applicant: U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    Inventor： U-in Chung ,  Jae-duk Kim ,  Chang-ki Hong

    IPC: H01L21/28 ,  H01L21/304 ,  H01L21/306 ,  H01L21/3205 ,  H01L21/768 ,  H01L23/532 ,  H01L21/44

    CPC classification number: H01L21/76831 ,  H01L21/76807 ,  H01L21/76843 ,  H01L21/76877 ,  H01L23/53238 ,  H01L23/53257 ,  H01L23/5329 ,  H01L2924/0002

    Abstract: A wire forming method for a semiconductor device includes the steps of depositing an insulation material on a semiconductor substrate and patterning the insulation material to form a first insulation layer, forming a lower capping layer on the first insulation layer, etching the lower capping layer and the first insulation layer to form a first contact hole that exposes a first part of the semiconductor substrate, forming a wire layer over the capping layer and the first part of the semiconductor substrate, performing a chemical and mechanical polishing (CMP) process with respect to the wire layer and the lower capping layer to expose the first insulation layer, forming a second insulation layer over the wire layer and the first insulation layer, and etching the first and second insulation layers to form a second contact hole that exposes a second part of the semiconductor substrate. The wire forming method can prevent the lifting of the wire layer, the splitting of the lower insulation layer, and the formation of a protrusion n the second contact hole.

    Abstract translation: 一种用于半导体器件的线形成方法包括以下步骤：在半导体衬底上沉积绝缘材料并图案化绝缘材料以形成第一绝缘层，在第一绝缘层上形成下覆盖层，蚀刻下封盖层和 第一绝缘层以形成暴露半导体衬底的第一部分的第一接触孔，在覆盖层和半导体衬底的第一部分上方形成引线层，对相对于第二绝缘层进行化学和机械抛光（CMP）处理 线层和下覆盖层以暴露第一绝缘层，在导线层和第一绝缘层上形成第二绝缘层，并蚀刻第一和第二绝缘层以形成第二接触孔，其暴露第二绝缘层的第二部分 半导体衬底。 线形成方法可以防止线层的提升，下绝缘层的分离，以及在第二接触孔处形成突起。

    Method of manufacturing high electron mobility transistor
    17.
    发明授权
    Method of manufacturing high electron mobility transistor 有权
    制造高电子迁移率晶体管的方法

    公开(公告)号：US08263449B2

    公开(公告)日：2012-09-11

    申请号：US13017361

    申请日：2011-01-31

    Applicant: Ki-ha Hong ,  U-In Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    Inventor： Ki-ha Hong ,  U-In Chung ,  Jai-kwang Shin ,  Jae-joon Oh ,  Jong-seob Kim ,  Hyuk-soon Choi ,  In-jun Hwang

    IPC: H01L21/338

    CPC classification number: H01L29/402 ,  H01L29/0891 ,  H01L29/66462 ,  H01L29/7786

    Abstract: A method of manufacturing a High Electron Mobility Transistor (HEMT) may include forming first and second material layers having different lattice constants on a substrate, forming a source, a drain, and a gate on the second material layer, and changing the second material layer between the gate and the drain into a different material layer, or changing a thickness of the second material layer, or forming a p-type semiconductor layer on the second material layer. The change in the second material layer may occur in an entire region of the second material layer between the gate and the drain, or only in a partial region of the second material layer adjacent to the gate. The p-type semiconductor layer may be formed on an entire top surface of the second material layer between the gate and the drain, or only on a partial region of the top surface adjacent to the gate.

    Abstract translation: 制造高电子迁移率晶体管（HEMT）的方法可以包括在衬底上形成具有不同晶格常数的第一和第二材料层，在第二材料层上形成源极，漏极和栅极，以及改变第二材料层 在栅极和漏极之间形成不同的材料层，或改变第二材料层的厚度，或在第二材料层上形成p型半导体层。 第二材料层的变化可以在栅极和漏极之间的第二材料层的整个区域中发生，或者仅在与栅极相邻的第二材料层的部分区域中发生。 p型半导体层可以形成在栅极和漏极之间的第二材料层的整个顶表面上，或者仅形成在与栅极相邻的顶表面的部分区域上。

    Methods of fabricating vertical channel field effect transistors having insulating layers thereon
    19.
    发明授权
    Methods of fabricating vertical channel field effect transistors having insulating layers thereon 有权
    制造其上具有绝缘层的垂直沟道场效应晶体管的方法

    公开(公告)号：US07459359B2

    公开(公告)日：2008-12-02

    申请号：US11556804

    申请日：2006-11-06

    Applicant: Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    Inventor： Tai-Su Park ,  Eui-Joon Yoon ,  U-In Chung ,  Si-Young Choi ,  Jong-Ho Lee

    IPC: H01L21/336 ,  H01L21/8234

    CPC classification number: H01L29/7851 ,  H01L29/66795 ,  H01L29/7854

    Abstract: A method of forming a field effect transistor includes forming a vertical channel protruding from a substrate including a source/drain region junction between the vertical channel and the substrate, and forming an insulating layer extending on a side wall of the vertical channel toward the substrate to beyond the source/drain region junction. The method may also include forming a nitride layer extending on the side wall away from the substrate to beyond the insulating layer, forming a second insulating layer extending on the side wall that is separated from the channel by the nitride layer, and forming a gate electrode extending on the side wall toward the substrate to beyond the source/drain region junction.

    Abstract translation: 形成场效应晶体管的方法包括形成从包括垂直沟道和衬底之间的源极/漏极区域的衬底突出的垂直沟道，并且形成在垂直沟道的侧壁上朝向衬底延伸的绝缘层， 超出源/漏区结。 该方法还可以包括在侧壁上形成远离衬底延伸到绝缘层的氮化物层，形成在侧壁上延伸的第二绝缘层，所述第二绝缘层通过氮化物层从沟道分离，并形成栅电极 在侧壁上朝向衬底延伸超过源/漏区结。

    Oxidation Treatment Apparatus and Method
    20.
    发明申请
    Oxidation Treatment Apparatus and Method 审中-公开
    氧化处理装置及方法

    公开(公告)号：US20070134415A1

    公开(公告)日：2007-06-14

    申请号：US11563980

    申请日：2006-11-28

    Applicant: Ki-Hyun Hwang ,  U-In Chung ,  Yu-Gyun Shin ,  Jae-Young Ahn ,  Jin-Gyun Kim

    Inventor： Ki-Hyun Hwang ,  U-In Chung ,  Yu-Gyun Shin ,  Jae-Young Ahn ,  Jin-Gyun Kim

    IPC: C23C16/00 ,  B05D3/04 ,  B05D7/00 ,  B05D1/02

    CPC classification number: H01L21/02233 ,  H01L21/31654

    Abstract: An oxidation treatment apparatus for oxidizing a surface of a substrate includes a process chamber for performing a process, a boat supporting the substrate and disposed in the process chamber during the process and a first ozone supply unit supplying ozone to the process chamber. The first ozone supply unit includes an ozone generator disposed at an exterior of the process chamber and an ozone spray nozzle disposed in the process chamber to spray the ozone supplied from the ozone generator into the process chamber.

    Abstract translation: 用于氧化基板表面的氧化处理装置包括处理过程的处理室，支撑基板的船，并且在处理过程中设置在处理室中，以及向处理室供应臭氧的第一臭氧供给单元。 第一臭氧供应单元包括设置在处理室外部的臭氧发生器和设置在处理室中的臭氧喷嘴，以将从臭氧发生器供应的臭氧喷射到处理室中。

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