公开(公告)号：US07598100B2

公开(公告)日：2009-10-06

申请号：US11719112

申请日：2004-11-18

Applicant: Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

Inventor： Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka

IPC: H01L21/00 ,  H01L31/26 ,  H01L21/66 ,  H01L21/82

CPC classification number: G01R1/0735 ,  G01R3/00

Abstract: As the thickness of the card holder for preventing warping of a multilayered wiring substrate 1 is increased, there occurs a problem that a thin film sheet 2 is buried in a card holder and secure contact between probes 7 and test pads cannot be realized. For its prevention, the thin film sheet 2 and a bonding ring 6 are bonded in a state where a tensile force is applied only to the central region IA of the thin film sheet 2, and a tensile force is not applied to an outer peripheral region OA. Then, the height of the bonding ring 6 defining the height up to the probe surface of the thin film sheet 2 is increased, thereby increasing the height up to the probe surface of the thin film sheet 2.

Abstract translation: 随着用于防止多层布线基板1翘曲的卡夹的厚度增加，存在薄膜片2被埋在卡夹中并且不能实现探针7和测试垫之间的牢固接触的​​问题。 为了防止，薄膜片2和接合环6在仅向薄膜片2的中心区域IA施加张力的状态下接合，并且拉伸力不施加到外围区域 OA。 然后，限定高达薄膜片2的探针表面的高度的接合环6的高度增加，从而增加高达薄膜片2的探针表面的高度。

公开(公告)号：US07537943B2

公开(公告)日：2009-05-26

申请号：US11866301

申请日：2007-10-02

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC: H01L21/66 ,  G01R31/26

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract translation: 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。

公开(公告)号：US20090017565A1

公开(公告)日：2009-01-15

申请号：US11816369

申请日：2005-03-11

Applicant: Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

Inventor： Akio Hasebe ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Yasuhiro Motoyama ,  Masayoshi Okamoto ,  Yasunori Narizuka ,  Naoki Okamoto

IPC: H01L21/66

CPC classification number: H01L24/10 ,  G01R31/2889 ,  H01L24/13 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05124 ,  H01L2224/05144 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/056 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01045 ,  H01L2924/01046 ,  H01L2924/01057 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/12036 ,  H01L2924/12041 ,  H01L2924/1306 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15788 ,  H01L2924/00 ,  H01L2924/00014

Abstract: A probe is contacted to a test pad, without destroying the circuit formed in the chip at the time of a probe test. Therefore, a load jig, a pressing tool, an elastomer, an adhesion ring, and a plunger are made into one by fixation with a nut and a bolt. The elastic force of the spring installed between the spring retaining jig and the load jig acts so that the member used as these one may be depressed toward pad PD. The thrust transmitted from the spring in a plunger to a thin films sheet is used only for the extension of a thin films sheet.

Abstract translation: 在探针测试时，探针与测试垫接触，而不会破坏芯片中形成的电路。 因此，通过用螺母和螺栓固定，将装载夹具，压制工具，弹性体，粘合环和柱塞制成一体。 安装在弹簧保持夹具和负载夹具之间的弹簧的弹力用于使得用作这些弹簧的构件可以朝向垫PD压下。 从弹簧传递到柱塞到薄膜片的推力仅用于薄膜片的延伸。

公开(公告)号：US20080096295A1

公开(公告)日：2008-04-24

申请号：US11866301

申请日：2007-10-02

Applicant: Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

Inventor： Akio HASEBE ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura

IPC: H01L21/66

CPC classification number: H01L22/34 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A technique of manufacturing a semiconductor integrated circuit device is provided for reducing the possibility of attachment of foreign matter to a membrane probe when performing probe inspection using the membrane probe formed by the manufacturing technique. A pressing member for pressing a membrane sheet includes a pressing pin receiving portion relatively disposed above for receiving the tip of a pressing pin of the plunger in a recess, and a membrane sheet pressing portion relatively disposed below. The membrane sheet pressing portion in contact with the membrane sheet has the minimum plane size to enable pressing of the entire surface of one chip of interest to be subjected to the probe inspection.

Abstract translation: 提供一种制造半导体集成电路器件的技术，用于在使用由该制造技术形成的膜探针进行探针检查时，减少将异物附着于膜探针的可能性。 用于挤压薄膜片的按压部件包括相对设置在上侧的压接销接收部，用于接收凹部中的柱塞的按压销的前端，以及相对设置在下方的膜片按压部。 与膜片接触的膜片按压部具有最小的平面尺寸，能够对要进行探头检查的一个感兴趣的芯片的整个表面进行按压。

公开(公告)号：US20070218572A1

公开(公告)日：2007-09-20

申请号：US11750371

申请日：2007-05-18

Applicant: Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

Inventor： Yuji Wada ,  Susumu Kasukabe ,  Takehiko Hasebe ,  Yasunori Narizuka ,  Akira Yabushita ,  Terutaka Mori ,  Akio Hasebe ,  Yasuhiro Motoyama ,  Teruo Shoji ,  Masakazu Sueyoshi

IPC: H01L21/66

CPC classification number: G01R1/07314 ,  G01R31/2872 ,  Y10T29/41 ,  Y10T29/49128 ,  Y10T29/49147 ,  Y10T29/49155 ,  Y10T29/49169 ,  Y10T29/49798

Abstract: The fabrication of a semiconductor integrated circuit device involves testing using a pushing mechanism that is constructed by forming, over the upper surface of a thin film probe, a reinforcing material having a linear expansion coefficient (thermal expansion coefficient) almost equal to that of a wafer to be tested; forming a groove in the reinforcing material above a contact terminal; placing an elastomer in the groove so that a predetermined amount projects out of the groove; and disposing a pusher and another elastomer to sandwich the pusher between the elastomers. With the use of such a probe, it is possible to improve the throughput of wafer-level electrical testing of a semiconductor integrated circuit.

Abstract translation: 半导体集成电路器件的制造包括使用推压机构进行测试，所述推压机构通过在薄膜探针的上表面上形成具有几乎等于晶片的线性膨胀系数（热膨胀系数）的增强材料而构成 待测 在接触端子上方的增强材料中形成凹槽; 将弹性体放置在所述槽中，使得预定量突出到所述凹槽中; 并且设置推进器和另一种弹性体以将推进器夹在弹性体之间。 通过使用这样的探针，可以提高半导体集成电路的晶片级电气测试的吞吐量。

公开(公告)号：US07198962B2

公开(公告)日：2007-04-03

申请号：US10411283

申请日：2003-04-11

Applicant: Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

Inventor： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC: G01R31/26 ,  H01L21/66 ,  H01L21/00 ,  H01L21/48

CPC classification number: G01R3/00 ,  G01R1/0735

Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

Abstract translation: 即使当大量区域中的多个探针通过将设置在膜中的探针压迫到晶片而将压力负载施加到压力构件的平面的多个位置时，负载的分散也可以保持在容许范围内 在作为半导体器件制造步骤之一的探针测试步骤/老化测试步骤中与晶片相对的一侧。 因此，可以提供通过同时探测大量集成电路或大尺寸集成电路来提高半导体器件的可靠性和生产率的半导体器件及其制造方法。

公开(公告)号：US06566150B2

公开(公告)日：2003-05-20

申请号：US10171695

申请日：2002-06-17

Applicant: Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

Inventor： Ryuji Kohno ,  Tetsuo Kumazawa ,  Makoto Kitano ,  Akihiko Ariga ,  Yuji Wada ,  Naoto Ban ,  Shuji Shibuya ,  Yasuhiro Motoyama ,  Kunio Matsumoto ,  Susumu Kasukabe ,  Terutaka Mori ,  Hidetaka Shigi ,  Takayoshi Watanabe

IPC: G01R3126

CPC classification number: G01R3/00 ,  G01R1/0735

Abstract: Dispersion of load may be kept within an allowance even when a plurality of probes in a large area are pressed in batch by pressing the probes provided in a membrane to a wafer by applying a pressure load to a plurality of places of a plane of pressure members on the side opposite from the wafer in a probe test step/burn-in test step which is one of semiconductor device manufacturing steps. It is then possible to provide semiconductor devices and a manufacturing method thereof which enhance the reliability and productivity of the semiconductor devices by probing a large number of integrated circuits or a large size integrated circuit in the same time.

公开(公告)号：US20110175634A1

公开(公告)日：2011-07-21

申请号：US13075666

申请日：2011-03-30

Applicant: Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

Inventor： Masayoshi Okamoto ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC: G01R31/3187 ,  G01R31/20

CPC classification number: H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

公开(公告)号：US20100304510A1

公开(公告)日：2010-12-02

申请号：US12853360

申请日：2010-08-10

Applicant: Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

Inventor： Masayoshi OKAMOTO ,  Yoshiaki Hasegawa ,  Yasuhiro Motoyama ,  Hideyuki Matsumoto ,  Shingo Yorisaki ,  Akio Hasebe ,  Ryuji Shibata ,  Yasunori Narizuka ,  Akira Yabushita ,  Toshiyuki Majima

IPC: H01L21/66

CPC classification number: H01L22/14 ,  G01R1/06711 ,  G01R1/06744 ,  G01R1/07307 ,  G01R3/00 ,  H01L2224/05553 ,  H01L2224/05554 ,  H01L2224/0603 ,  H01L2224/45144 ,  H01L2224/48453 ,  H01L2224/48463 ,  H01L2224/49171 ,  H01L2924/014 ,  H01L2924/3011 ,  H01L2924/00

Abstract: To permit electrical testing of a semiconductor integrated circuit device having test pads disposed at narrow pitches probes in a pyramid or trapezoidal pyramid form are formed from metal films formed by stacking a rhodium film and a nickel film successively. Via through-holes are formed in a polyimide film between interconnects and the metal films, and the interconnects are electrically connected to the metal films. A plane pattern of one of the metal films equipped with one probe and through-hole is obtained by turning a plane pattern of the other metal film equipped with the other probe and through-hole through a predetermined angle.

Abstract translation: 为了允许具有金字塔或梯形金字塔形式的窄间距探针设置的测试焊盘的半导体集成电路器件进行电气测试，是由依次层叠铑膜和镍膜而形成的金属膜形成的。 在互连和金属膜之间的聚酰亚胺膜中形成通孔，并且互连电连接到金属膜。 通过将配备有另一个探针和通孔的另一金属膜的平面图案转过预定角度，获得装配有一个探针和通孔的金属膜之一的平面图案。

公开(公告)号：US20100279502A1

公开(公告)日：2010-11-04

申请号：US12836580

申请日：2010-07-15

Applicant: Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

Inventor： Akio Hasebe ,  Yasuhiro Motoyama ,  Yasunori Narizuka ,  Seigo Nakamura ,  Kenji Kawakami

IPC: H01L21/768

CPC classification number: G01R3/00 ,  G01R1/07342

Abstract: A probe having a sufficient height is manufactured by selectively depositing, over the main surface of a wafer, a copper film in a region in which a metal film is to be formed and a region which will be outside an adhesion ring when a probe card is fabricated; forming the metal film, polyimide film, interconnect, another polyimide film, another interconnect and a further polyimide film; and then removing the wafer and copper film. According to the present invention, when probe testing is performed using a prober (thin film probe) having the probe formed in the above-described manner while utilizing the manufacturing technology of semiconductor integrated circuit devices, it is possible to prevent breakage of the prober and a wafer to be tested.

Abstract translation: 通过选择性地在晶片的主表面上沉积在要形成金属膜的区域中的铜膜和当探针卡是在粘合环外部时将在粘合环外部的区域，制造具有足够高度的探针 制造的 形成金属膜，聚酰亚胺膜，互连，另一聚酰亚胺膜，另一互连和另外的聚酰亚胺膜; 然后取出晶片和铜膜。 根据本发明，在利用半导体集成电路器件的制造技术的情况下，使用具有以上述方式形成的探针的探测器（薄膜探针）进行探针测试时，可以防止探测器的破损， 待测试的晶圆。