公开(公告)号：US11177254B2

公开(公告)日：2021-11-16

申请号：US16599360

申请日：2019-10-11

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Sanjay Natarajan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/822

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

公开(公告)号：US20200235104A1

公开(公告)日：2020-07-23

申请号：US16839392

申请日：2020-04-03

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Jianxin Lei ,  Wenting Hou ,  Mihaela Balseanu ,  Ning Li ,  Sanjay Natarajan ,  Gill Yong Lee ,  In Seok Hwang ,  Nobuyuki Sasaki ,  Sung-Kwan Kang

IPC: H01L27/108 ,  H01L21/3213 ,  H01L21/033

Abstract: Memory devices and methods of forming memory devices are described. The memory devices comprise a substrate with at least one film stack. The film stack comprises a polysilicon layer on the substrate; a bit line metal layer on the polysilicon layer; a cap layer on the bit line metal layer; and a hardmask on the cap layer. The memory device of some embodiments includes an optional barrier metal layer on the polysilicon layer and the bit line metal layer is on the barrier metal layer. Methods of forming electronic devices are described where one or more patterns are transferred through the films of the film stack to provide the bit line of a memory device.

公开(公告)号：US11705335B2

公开(公告)日：2023-07-18

申请号：US17724994

申请日：2022-04-20

Applicant: Applied Materials, Inc.

Inventor： Srinivas Gandikota ,  Abhijit Basu Mallick ,  Swaminathan Srinivasan ,  Rui Cheng ,  Susmit Singha Roy ,  Gaurav Thareja ,  Mukund Srinivasan ,  Sanjay Natarajan

IPC: H01L21/225 ,  H01L21/30 ,  H01L21/02 ,  H01L21/67

CPC classification number: H01L21/2257 ,  H01L21/02043 ,  H01L21/02164 ,  H01L21/30 ,  H01L21/67167

Abstract: Methods of doping a semiconductor material are disclosed. Some embodiments provide for conformal doping of three dimensional structures. Some embodiments provide for doping with high concentrations of boron for p-type doping.

公开(公告)号：US20220199804A1

公开(公告)日：2022-06-23

申请号：US17690193

申请日：2022-03-09

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L21/687 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L29/08

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US11295786B2

公开(公告)日：2022-04-05

申请号：US16779830

申请日：2020-02-03

Applicant: Applied Materials, Inc.

Inventor： Chang Seok Kang ,  Tomohiko Kitajima ,  Gill Yong Lee ,  Sanjay Natarajan ,  Sung-Kwan Kang ,  Lequn Liu

IPC: H01L27/108 ,  H01L21/8242 ,  G11C5/06

Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.

公开(公告)号：US20220005937A1

公开(公告)日：2022-01-06

申请号：US17354251

申请日：2021-06-22

Applicant: Applied Materials, Inc.

Inventor： Michael Stolfi ,  Myungsun Kim ,  Benjamin Colombeau ,  Sanjay Natarajan

IPC: H01L29/66 ,  H01L29/423 ,  H01L29/06

Abstract: Horizontal gate-all-around devices and methods of manufacturing same are described. The hGAA devices comprise a trimmed semiconductor material between source regions and drain regions of the device. The method includes selectively isotropically etching semiconductor material layers between source regions and drain regions of an electronic device.

公开(公告)号：US20200013878A1

公开(公告)日：2020-01-09

申请号：US16502555

申请日：2019-07-03

Applicant: Applied Materials, Inc.

Inventor： Benjamin Colombeau ,  Tushar Mandrekar ,  Patricia M. Liu ,  Suketu Arun Parikh ,  Matthias Bauer ,  Dimitri R. Kioussis ,  Sanjay Natarajan ,  Abhishek Dube

IPC: H01L29/66 ,  H01L29/08 ,  H01L29/78 ,  H01L21/02 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/423 ,  H01L29/786 ,  H01L21/67 ,  H01L21/677 ,  H01L21/687

Abstract: A finFET device includes a doped source and/or drain extension that is disposed between a gate spacer of the finFET and a bulk semiconductor portion of the semiconductor substrate on which the n-doped or p-doped source or drain extension is disposed. The doped source or drain extension is formed by a selective epitaxial growth (SEG) process in a cavity formed proximate the gate spacer. After formation of the cavity, advanced processing controls (APC) (i.e., integrated metrology) is used to determine the distance of recess, without exposing the substrate to an oxidizing environment. The isotropic etch process, the metrology, and selective epitaxial growth may be performed in the same platform.

公开(公告)号：US10529602B1

公开(公告)日：2020-01-07

申请号：US16189487

申请日：2018-11-13

Applicant: APPLIED MATERIALS, INC.

Inventor： Priyadarshi Panda ,  Gill Lee ,  Srinivas Gandikota ,  Sung-Kwan Kang ,  Sanjay Natarajan

IPC: H01L21/67

Abstract: Methods and apparatuses for substrate fabrication are provided herein. The apparatus, for example, can include a cluster tool including a vacuum transfer module (VTM) configured to receive, under vacuum conditions, a silicon substrate with a polysilicon plug (poly plug) and transfer, without vacuum break, the substrate to and from a plurality of processing chambers each independently connected to the VTM for performing a corresponding one of a plurality of DRAM bit line processes on the substrate, the plurality of processing chambers comprising a pre-cleaning chamber configured to remove native oxide from a surface of the substrate, a barrier metal deposition chamber configured to deposit the barrier metal on the surface of the poly plug on the silicon substrate, a barrier layer deposition chamber configured to deposit at least one material on the surface of the barrier metal, a bit line metal deposition chamber configured to deposit at least one material on the surface of the barrier layer, and a hard mask deposition chamber configured to deposit at least one material on the surface of the bit line metal.

公开(公告)号：US11682668B2

公开(公告)日：2023-06-20

申请号：US17500003

申请日：2021-10-13

Applicant: Applied Materials, Inc.

Inventor： Suketu Arun Parikh ,  Sanjay Natarajan

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/822

CPC classification number: H01L27/088 ,  H01L21/8221 ,  H01L21/823481

Abstract: Logic devices and methods of forming logic devices are described. An epitaxial channel is formed orthogonally to a horizontal plane of a substrate surface with a stack or horizontal transistors on the substrate surface. The first horizontal transistor having a first length and a first step, the second horizontal transistor having a second length and a second step and a third horizontal transistor has a third length and a third step. Each of the horizontal transistors is separated from adjacent layers by a horizontal isolation layer.

公开(公告)号：US11621266B2

公开(公告)日：2023-04-04

申请号：US17522448

申请日：2021-11-09

Applicant: Applied Materials, Inc.

Inventor： Priyadarshi Panda ,  Seshadri Ganguli ,  Sang Ho Yu ,  Sung-Kwan Kang ,  Gill Yong Lee ,  Sanjay Natarajan ,  Rajib Lochan Swain ,  Jorge Pablo Fernandez

IPC: H01L21/67 ,  H01L27/108

Abstract: Methods of forming memory devices are described. Some embodiments of the disclosure utilize a low temperature anneal process to reduce bottom voids and seams in low melting point, low resistance metal buried word lines. Some embodiments of the disclosure utilize a high density dielectric cap during a high temperature anneal process to reduce bottom voids in buried word lines.