公开(公告)号：US07202764B2

公开(公告)日：2007-04-10

申请号：US10604278

申请日：2003-07-08

申请人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

发明人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

IPC分类号： H01H51/22

CPC分类号： H01H59/0009 ,  H01H2001/0052 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

摘要翻译： 描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。 集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400℃）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。

公开(公告)号：US07829427B2

公开(公告)日：2010-11-09

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/20

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; 在（d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US07068138B2

公开(公告)日：2006-06-27

申请号：US10768773

申请日：2004-01-29

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01F27/24

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： An inductor and a method of forming and the inductor, the method including: (a) providing a semiconductor substrate; (b) forming a dielectric layer on a top surface of the substrate; (c) forming a lower trench in the dielectric layer; (d) forming a resist layer on a top surface of the dielectric layer; (e) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and (f) completely filling the lower trench at least partially filling the upper trench with a conductor in order to form the inductor. The inductor including a top surface, a bottom surface and sidewalls, a lower portion of said inductor extending a fixed distance into a dielectric layer formed on a semiconductor substrate and an upper portion extending above said dielectric layer; and means to electrically contact said inductor.

摘要翻译： 一种电感器及其形成方法和电感器，所述方法包括：（a）提供半导体衬底; （b）在所述基板的顶表面上形成电介质层; （c）在介电层中形成下沟槽; （d）在介电层的顶表面上形成抗蚀剂层; （e）在所述抗蚀剂层中形成上沟槽，所述上沟槽对准所述下沟槽，所述上沟槽的底部通向所述下沟槽; 和（f）用导体完全填充下沟槽至少部分地填充上沟槽，以形成电感器。 所述电感器包括顶表面，底表面和侧壁，所述电感器的下部将固定距离延伸到形成在半导体衬底上的电介质层和在所述电介质层上方延伸的上部; 以及用于电接触所述电感器的装置。

公开(公告)号：US08421220B2

公开(公告)日：2013-04-16

申请号：US13365505

申请日：2012-02-03

申请人： John Ulrich Knickerbocker ,  John H. Magerlein

发明人： John Ulrich Knickerbocker ,  John H. Magerlein

IPC分类号： H01L23/34

CPC分类号： H01L23/34 ,  G01R31/2877 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/544 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

摘要翻译： 芯片封装包括：基板; 与硅载体接触的多个导电连接; 设置在所述衬底上方的预制形状的硅载体，所述硅载体包括：多个通过硅通孔，用于提供通过所述硅载体与所述芯片的互连; 液体微通道进行冷却; 流过微通道的液体冷却剂; 以及与一个或多个芯片或芯片堆叠的互连。

公开(公告)号：US08097492B2

公开(公告)日：2012-01-17

申请号：US12344095

申请日：2008-12-24

申请人： John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

发明人： John H. Magerlein ,  Chirag S. Patel ,  Edmund J. Sprogis ,  Herbert I. Stoller

IPC分类号： H01L21/50

CPC分类号： H01L21/486 ,  H01L21/6835 ,  H01L21/6836 ,  H01L21/76898 ,  H01L23/147 ,  H01L24/16 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68345 ,  H01L2221/68354 ,  H01L2221/68363 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/16237 ,  H01L2924/00014 ,  H01L2924/01046 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/00 ,  H01L2224/0401 ,  H01L2924/00012

摘要： A Silicon Based Package (SBP) is formed starting with a thick wafer, which serves as the base for the SBP, composed of silicon which has a first surface and a reverse surface which are planar. Then form an interconnection structure including metal capture structures in contact with the first surface and multilayer conductor patterns over the first surface. Form a temporary bond between the SBP and a wafer holder, with the wafer holder being a rigid structure. Thin the reverse side of the wafer to a desired thickness to form an Ultra Thin Silicon Wafer (UTSW) for the SBP. Form via holes with tapered or vertical sidewalls, which extend through the UTSW to reach the metal capture structures. Then form metal pads in the via holes which extend through the UTSW, making electrical contact to the metal capture structures. Then bond the metal pads in the via holes to pads of a carrier.

摘要翻译： 基于硅的封装（SBP）由从作为SBP的基底的厚晶片开始形成，该基板由具有平坦的第一表面和反面的硅组成。 然后形成包括与第一表面接触的金属捕获结构和在第一表面上的多层导体图案的互连结构。 在SBP和晶片保持器之间形成临时结合，晶片保持器是刚性结构。 将晶圆的反面变薄到所需的厚度，以形成用于SBP的超薄硅晶片（UTSW）。 通过具有锥形或垂直侧壁的孔形成，其延伸穿过UTSW以到达金属捕获结构。 然后在穿过UTSW的通孔中形成金属焊盘，使其与金属捕获结构电接触。 然后将通孔中的金属焊盘接合到载体的焊盘。

公开(公告)号：US20100047990A1

公开(公告)日：2010-02-25

申请号：US12612743

申请日：2009-11-05

申请人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

发明人： Daniel C. Edelstein ,  Panayotis C. Andricacos ,  John M. Cotte ,  Hariklia Deligianni ,  John H. Magerlein ,  Kevin S. Petrarca ,  Kenneth J. Stein ,  Richard P. Volant

IPC分类号： H01L21/02

CPC分类号： H01L24/12 ,  H01L23/5227 ,  H01L23/53238 ,  H01L24/03 ,  H01L24/05 ,  H01L27/08 ,  H01L28/10 ,  H01L2224/0401 ,  H01L2224/04042 ,  H01L2224/05007 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05084 ,  H01L2224/05555 ,  H01L2224/05557 ,  H01L2224/05558 ,  H01L2224/05624 ,  H01L2224/05644 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13023 ,  H01L2224/13099 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/48624 ,  H01L2224/48644 ,  H01L2224/48724 ,  H01L2224/48744 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01028 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01042 ,  H01L2924/0105 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04953 ,  H01L2924/05042 ,  H01L2924/14 ,  H01L2924/19042 ,  H01L2924/30107 ,  H01L2924/00014 ,  H01L2924/00

摘要： A method of forming an inductor. The method including: (a) forming a dielectric layer on a top surface of a substrate; after (a), (b) forming a lower trench in the dielectric layer; after (b), (c) forming a resist layer on a top surface of the dielectric layer; after (c), (d) forming an upper trench in the resist layer, the upper trench aligned to the lower trench, a bottom of the upper trench open to the lower trench; and after (d), (e) completely filling the lower trench and at least partially filling the upper trench with a conductor in order to form the inductor.

摘要翻译： 一种形成电感器的方法。 该方法包括：（a）在基板的顶表面上形成电介质层; （a）之后，（b）在介电层中形成下沟槽; （b）之后，（c）在介电层的顶表面上形成抗蚀剂层; 在（c）之后，（d）在抗蚀剂层中形成上沟槽，上沟槽与下沟槽对准，上沟槽的底部通向下沟槽; （d）之后，（e）完全填充下沟槽并且用导体至少部分地填充上沟槽以形成电感器。

公开(公告)号：US07581314B2

公开(公告)日：2009-09-01

申请号：US11358823

申请日：2006-02-21

申请人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

发明人： Hariklia Deligianni ,  Panayotis Andricacos ,  L. Paivikki Buchwalter ,  John M. Cotte ,  Christopher Jahnes ,  Mahadevaiyer Krishnan ,  John H. Magerlein ,  Kenneth Stein ,  Richard P. Volant ,  James A. Tornello ,  Jennifer Lund

IPC分类号： H01K3/10

CPC分类号： H01H59/0009 ,  H01H2001/0052 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： A semiconductor micro-electromechanical system (MEMS) switch provided with noble metal contacts that act as an oxygen barrier to copper electrodes is described. The MEMS switch is fully integrated into a CMOS semiconductor fabrication line. The integration techniques, materials and processes are fully compatible with copper chip metallization processes and are typically, a low cost and a low temperature process (below 400° C.). The MEMS switch includes: a movable beam within a cavity, the movable beam being anchored to a wall of the cavity at one or both ends of the beam; a first electrode embedded in the movable beam; and a second electrode embedded in an wall of the cavity and facing the first electrode, wherein the first and second electrodes are respectively capped by the noble metal contact.

摘要翻译： 描述了提供有作为铜电极的氧阻隔的贵金属触点的半导体微机电系统（MEMS）开关。 MEMS开关完全集成到CMOS半导体制造线中。 集成技术，材料和工艺完全兼容铜芯片金属化工艺，通常是低成本和低温工艺（低于400℃）。 MEMS开关包括：在空腔内的可移动光束，可移动光束在光束的一端或两端锚定到空腔的壁; 嵌入可移动光束中的第一电极; 以及第二电极，其嵌入在所述空腔的壁中并且面向所述第一电极，其中所述第一和第二电极分别被所述贵金属接触物覆盖。

公开(公告)号：US08110415B2

公开(公告)日：2012-02-07

申请号：US12062055

申请日：2008-04-03

申请人： John Ulrich Knickerbocker ,  John H. Magerlein

发明人： John Ulrich Knickerbocker ,  John H. Magerlein

IPC分类号： H01L21/66

CPC分类号： H01L23/34 ,  G01R31/2877 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/544 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

摘要翻译： 芯片封装包括：基板; 与硅载体接触的多个导电连接; 设置在所述衬底上方的预制形状的硅载体，所述硅载体包括：多个通过硅通孔，用于提供通过所述硅载体与所述芯片的互连; 液体微通道进行冷却; 流过微通道的液体冷却剂; 以及与一个或多个芯片或芯片堆叠的互连。

公开(公告)号：US20090251862A1

公开(公告)日：2009-10-08

申请号：US12062055

申请日：2008-04-03

申请人： John Ulrich Knickerbocker ,  John H. Magerlein

发明人： John Ulrich Knickerbocker ,  John H. Magerlein

IPC分类号： H05K7/20 ,  H01L21/66

CPC分类号： H01L23/34 ,  G01R31/2877 ,  H01L23/473 ,  H01L23/5384 ,  H01L23/544 ,  H01L25/0652 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/17181 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/0652 ,  H01L2225/06572 ,  H01L2225/06589 ,  H01L2924/01019 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/00

摘要： A chip package includes: a substrate; a plurality of conductive connections in contact with the silicon carrier; a silicon carrier in a prefabricated shape disposed above the substrate, the silicon carrier including: a plurality of through silicon vias for providing interconnections through the silicon carrier to the chip; liquid microchannels for cooling; a liquid coolant flowing through the microchannels; and an interconnect to one or more chips or chip stacks.

摘要翻译： 芯片封装包括：基板; 与硅载体接触的多个导电连接; 设置在所述衬底上方的预制形状的硅载体，所述硅载体包括：多个通过硅通孔，用于提供通过所述硅载体与所述芯片的互连; 液体微通道进行冷却; 流过微通道的液体冷却剂; 以及与一个或多个芯片或芯片堆叠的互连。