公开(公告)号：US20140115428A1

公开(公告)日：2014-04-24

申请号：US14144957

申请日：2013-12-31

Applicant: Apple Inc.

Inventor： Anthony Fai

IPC: G06F11/10

CPC classification number: G06F11/1068 ,  G06F11/076 ,  G06F11/106 ,  G11C11/406 ,  G11C11/40618 ,  G11C16/3418 ,  G11C29/08

Abstract: System and methods for proactively refreshing portions of a nonvolatile memory including a memory system that proactively refreshes a portion of nonvolatile memory based on data associated with the portion. The data may include the time elapsed since the portion was last refreshed, the number of times the portion has been cycled, and the average operating temperature of the nonvolatile memory. A portion of nonvolatile memory, when meeting certain criteria determined from the data, may be proactively refreshed during a downtime when the nonvolatile memory is not otherwise being accessed.

Abstract translation: 用于主动刷新非易失性存储器的部分的系统和方法，所述非易失性存储器包括基于与所述部分相关联的数据来主动刷新非易失性存储器的一部分的存储器系统。 数据可以包括自该部分最后刷新以来经过的时间，该部分已循环的次数以及该非易失性存储器的平均工作温度。 当非易失性存储器未被访问时，非易失性存储器的一部分当满足从数据确定的某些标准时可以在停机期间主动刷新。

公开(公告)号：US20130073800A1

公开(公告)日：2013-03-21

申请号：US13676729

申请日：2012-11-14

Applicant: APPLE INC.

Inventor： Vadim Khmelnitsky ,  Nir Jacob Wakrat ,  Tahoma Toelkes ,  Daniel Jeffrey Post ,  Anthony Fai

IPC: G06F12/02

CPC classification number: G06F12/0246

Abstract: Multipage preparation commands for non-volatile memory systems are disclosed. The multipage preparation commands supply data that can be used to prepare a non-volatile memory device for forthcoming multipage program operations. A host controller can use the commands ahead of a multipage program operation to optimize usage of a multipage program command. The non-volatile memory device can use the commands to configure the non-volatile memory in preparation for a subsequent operation, such as changing a command order or using the most optimized command set for the subsequent operation.

Abstract translation: 公开了用于非易失性存储器系统的多位准备命令。 多功能准备命令提供可用于准备非易失性存储器设备的数据，用于即将进行的多页程序操作。 主机控制器可以使用多页面程序操作之前的命令来优化多页面程序命令的使用。 非易失性存储器件可以使用这些命令来配置非易失性存储器以准备随后的操作，例如改变命令顺序或使用用于后续操作的最优化的命令集。

公开(公告)号：US20170005056A1

公开(公告)日：2017-01-05

申请号：US15266752

申请日：2016-09-15

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

公开(公告)号：US20130283081A1

公开(公告)日：2013-10-24

申请号：US13918240

申请日：2013-06-14

Applicant: Apple Inc.

Inventor： Nir Jacob Wakrat ,  Anthony Fai ,  Matthew Byom

IPC: G06F1/32

CPC classification number: G06F1/3275 ,  G06F1/3225 ,  Y02D10/13 ,  Y02D10/14

Abstract: In a non-volatile memory system, physically separate power rails are provided from a host system to a NVM device for independently power cycling a controller and memory array in the NVM device. The controller of the NVM device can send a power cycle request signal to the host system over a host channel, or updates a status register in the NVM device. The host system receives and decodes the power cycle request signal, or reads the status register, and performs the power cycle request, which can include power cycling the controller or the memory array in the NVM device, or both. The power cycle request can be based on a power state of the non-volatile memory system, which can be managed by the controller or the host system, or both.

Abstract translation: 在非易失性存储器系统中，物理上分离的电源轨从主机系统提供给NVM设备，用于独立地对NVM设备中的控制器和存储器阵列进行电力循环。 NVM设备的控制器可以通过主机通道向主机系统发送电源循环请求信号，或更新NVM设备中的状态寄存器。 主机系统接收并解码电源周期请求信号，或读取状态寄存器，并执行电源循环请求，其中可以包括对NVM设备中的控制器或存储器阵列进行电源循环，或两者兼而有之。 功率循环请求可以基于非易失性存储器系统的功率状态，其可以由控制器或主机系统管理，或两者兼而有之。

公开(公告)号：US20170162546A1

公开(公告)日：2017-06-08

申请号：US15435719

申请日：2017-02-17

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L25/065 ,  H01L23/498 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

公开(公告)号：US09583452B2

公开(公告)日：2017-02-28

申请号：US15266752

申请日：2016-09-15

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L23/00 ,  H01L25/065

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

公开(公告)号：US09472243B2

公开(公告)日：2016-10-18

申请号：US14330774

申请日：2014-07-14

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Nicholas C. Seroff

IPC: G11C5/06 ,  H01L25/065 ,  H01L25/18 ,  H01L25/00 ,  H01L23/00 ,  H01L23/522 ,  H01L23/552 ,  H01L25/16 ,  H01L29/06

CPC classification number: G11C5/06 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2541 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/49175 ,  H01L2225/06537 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/30107 ,  H01L2924/00

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract translation: 为叠层半导体存储器件提供系统和方法。 层叠的半导体存储器件可以包括非易失性存储器控制器，以堆叠构造布置的多个非易失性存储器管芯和封装衬底。 存储器控制器和存储器管芯可以通过延伸穿过封装衬底的通孔彼此耦合。 可以使用垂直互连处理来将非易失性存储器管芯彼此以及其它系统部件电连接。 存储器控制器可以倒装芯片接合到外部电路，例如另一个半导体器件或印刷电路板。

公开(公告)号：US09087846B2

公开(公告)日：2015-07-21

申请号：US13801722

申请日：2013-03-13

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/538 ,  H01L23/498 ,  H01L25/065 ,  H01L25/18

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。

公开(公告)号：US20140321189A1

公开(公告)日：2014-10-30

申请号：US14330774

申请日：2014-07-14

Applicant: Apple Inc.

Inventor： Anthony Fai ,  Nicholas C. Seroff

IPC: G11C5/06 ,  H01L23/552 ,  H01L23/522 ,  H01L23/00

CPC classification number: G11C5/06 ,  G11C5/063 ,  H01L23/5226 ,  H01L23/552 ,  H01L24/17 ,  H01L24/24 ,  H01L24/25 ,  H01L25/0657 ,  H01L25/16 ,  H01L25/18 ,  H01L25/50 ,  H01L29/0657 ,  H01L2224/24051 ,  H01L2224/24146 ,  H01L2224/24226 ,  H01L2224/244 ,  H01L2224/245 ,  H01L2224/25175 ,  H01L2224/2541 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48147 ,  H01L2224/49175 ,  H01L2225/06537 ,  H01L2225/06551 ,  H01L2225/06565 ,  H01L2924/30107 ,  H01L2924/00

Abstract: Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.

Abstract translation: 为叠层半导体存储器件提供系统和方法。 堆叠的半导体存储器件可以包括非易失性存储器控制器，以堆叠配置布置的多个非易失性存储器管芯和封装衬底。 存储器控制器和存储器管芯可以通过延伸穿过封装衬底的通孔彼此耦合。 可以使用垂直互连处理来将非易失性存储器管芯彼此以及其它系统部件电连接。 存储器控制器可以倒装芯片接合到外部电路，例如另一个半导体器件或印刷电路板。

公开(公告)号：US20140264906A1

公开(公告)日：2014-09-18

申请号：US13801722

申请日：2013-03-13

Applicant: APPLE INC.

Inventor： Anthony Fai ,  Evan R. Boyle ,  Zhiping Yang ,  Zhonghua Wu

IPC: H01L23/538

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/56 ,  H01L23/49811 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49838 ,  H01L23/5283 ,  H01L23/5286 ,  H01L23/5384 ,  H01L23/552 ,  H01L23/60 ,  H01L24/06 ,  H01L24/14 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/18 ,  H01L25/50 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06151 ,  H01L2224/06177 ,  H01L2224/1405 ,  H01L2224/1414 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45124 ,  H01L2224/45144 ,  H01L2224/45147 ,  H01L2224/48091 ,  H01L2224/48106 ,  H01L2224/48227 ,  H01L2224/73253 ,  H01L2224/73257 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2225/0651 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06527 ,  H01L2225/06537 ,  H01L2225/06548 ,  H01L2225/06555 ,  H01L2225/06562 ,  H01L2924/00014 ,  H01L2924/1443 ,  H01L2924/15311 ,  H01L2924/15312 ,  H01L2924/15313 ,  H01L2924/3025 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: Systems and methods are provided for stacked semiconductor memory packages. Each package can include an integrated circuit (“IC”) package substrate capable of transmitting data to memory dies stacked within the package over two channels. Each channel can be located on one side of the IC package substrate, and signals from each channel can be routed to the memory dies from their respective sides.

Abstract translation: 为层叠半导体存储器封装提供了系统和方法。 每个封装可以包括集成电路（“IC”）封装基板，能够通过两个通道将数据传输到堆叠在封装内的存储器管芯。 每个通道可以位于IC封装衬底的一侧，并且来自每个通道的信号可以从它们各自的侧面被引导到存储器管芯。