公开(公告)号：US20160167949A1

公开(公告)日：2016-06-16

申请号：US14568845

申请日：2014-12-12

Applicant: Apple Inc.

Inventor： Tongbi Jiang ,  Jie-Hua Zhao ,  Peter G. Hartwell

IPC: B81B7/00

CPC classification number: B81B7/0048 ,  B81B2207/012 ,  B81B2207/07 ,  B81B2207/99 ,  B81C3/001 ,  B81C2203/035 ,  B81C2203/07

Abstract: MEMS packages, modules, and methods of fabrication are described. In an embodiment, a MEMS package includes a MEMS die and an IC die mounted on a front side of a surface mount substrate, and a molding compound encapsulating the IC die and the MEMS die on the front side of the surface mount substrate. In an embodiment, a landing pad arrangement on a back side of the surface mount substrate forms and anchor plane area for bonding the surface mount substrate to a module substrate that is not directly beneath the MEMS die.

公开(公告)号：US20160071807A1

公开(公告)日：2016-03-10

申请号：US14518887

申请日：2014-10-20

Applicant: Apple Inc.

Inventor： Jun Chung Hsu ,  Jie-Hua Zhao

IPC: H01L23/00 ,  H01L23/498

CPC classification number: H01L23/562 ,  H01L23/3128 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/49866 ,  H01L2224/16225 ,  H01L2924/15311 ,  H01L2924/18161

Abstract: A methodology for addressing package warpage is described. In an embodiment a package includes a die mounted on a wiring board. Portion of a metal plane within the wiring board includes a reduced portion, characterized by a reduced thickness that is less than a baseline thickness.

Abstract translation: 描述了解决包装翘曲的方法。 在一个实施例中，封装包括安装在布线板上的管芯。 线路板内的金属平面的一部分包括减少的部分，其特征在于小于基线厚度的厚度减小。

公开(公告)号：US09263426B2

公开(公告)日：2016-02-16

申请号：US14593317

申请日：2015-01-09

Applicant: Apple Inc.

Inventor： Jie-Hua Zhao ,  Yizhang Yang ,  Jun Zhai ,  Chih-Ming Chung

IPC: H01L21/44 ,  H01L21/48 ,  H01L25/00 ,  H01L25/10 ,  H01L23/31 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L23/3128 ,  H01L24/16 ,  H01L24/32 ,  H01L24/48 ,  H01L24/73 ,  H01L25/105 ,  H01L2224/16225 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2225/0651 ,  H01L2225/06562 ,  H01L2225/1023 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15311 ,  H01L2924/15331 ,  H01L2924/181 ,  H01L2924/1815 ,  H01L2924/18161 ,  H01L2924/3511 ,  H01L2924/37001 ,  Y02P80/30 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.

公开(公告)号：US20240421126A1

公开(公告)日：2024-12-19

申请号：US18598938

申请日：2024-03-07

Applicant: Apple Inc.

Inventor： Chi Nung Ni ,  Wei Chen ,  Weiming Chris Chen ,  Vidhya Ramachandran ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Myung Jin Yim ,  Chih-Ming Chung ,  Jun Zhai ,  Young Doo Jeon ,  Seungjae Lee

IPC: H01L25/065 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31 ,  H01L23/528 ,  H01L23/538 ,  H01L23/58 ,  H01L29/06

Abstract: Integrated circuit (IC) structures, electronic modules, and methods of fabrication are described in which direct bonded interfaces are removed at corners or edges to counteract the potential for non-bonding or delamination. This can be accomplished during singulation, in which a side recess is formed through an entire thickness of an electronic component and into a direct bonded die, followed by final singulation of the IC structure.

公开(公告)号：US20240395686A1

公开(公告)日：2024-11-28

申请号：US18324612

申请日：2023-05-26

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Kunzhong Hu ,  Arun Sasi ,  Balaji Nandhivaram Muthuraman ,  Zezhou Liu

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

Abstract: Electronic packages and electronic systems are described in which a package redistribution layer of the electronic package includes structural features such a via line connections to reduce stress concentration, particularly when the package redistribution layer is formed of organic dielectric materials.

公开(公告)号：US20240249989A1

公开(公告)日：2024-07-25

申请号：US18158090

申请日：2023-01-23

Applicant: Apple Inc.

Inventor： Wei Chen ,  Balaji Nandhivaram Muthuraman ,  Arun Sasi ,  Jie-Hua Zhao ,  Suk-Kyu Ryu ,  Jun Zhai ,  Dominic Morache ,  Young Doo Jeon

IPC: H01L23/31 ,  H01L23/00 ,  H01L23/34

CPC classification number: H01L23/3157 ,  H01L23/34 ,  H01L24/16 ,  H01L24/17 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/17055 ,  H01L2924/10162 ,  H01L2924/1811 ,  H01L2924/182

Abstract: Microelectronic structures with selectively applied underfill material and/or edge bond material are described. In an embodiment, isolated underfill regions and/or edge bond regions are applied to adjacent to one or more edges of an electronic device and form a plurality of vent openings along the one or more edges.

公开(公告)号：US20230317624A1

公开(公告)日：2023-10-05

申请号：US18058991

申请日：2022-11-28

Applicant: Apple Inc.

Inventor： Wei Chen ,  Yi Xu ,  Jie-Hua Zhao ,  Jun Zhai

IPC: H01L23/538 ,  H01L23/31 ,  H01L25/065 ,  H01L25/18 ,  H01L23/00

CPC classification number: H01L23/5386 ,  H01L23/3128 ,  H01L23/5383 ,  H01L23/562 ,  H01L25/0655 ,  H01L25/18 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/16227 ,  H01L2224/48225

Abstract: Microelectronic packages and methods of fabrication are described. In an embodiment, a redistribution layer spans across multiple components, and includes a region of patterned wiring traces that may mitigate stress in the RDL between the multiple components.

公开(公告)号：US20230147273A1

公开(公告)日：2023-05-11

申请号：US17821920

申请日：2022-08-24

Applicant: Apple Inc.

Inventor： Brett W. Degner ,  Jie-Hua Zhao ,  Kristopher P. Laurent ,  Michael E. Leclerc ,  Rangaraj Dhanasekaran ,  Simon J. Trivett

IPC: H01L23/00 ,  H01L25/16 ,  H01L25/065 ,  H01L23/498 ,  H01L21/48

CPC classification number: H01L23/562 ,  H01L25/16 ,  H01L25/0655 ,  H01L24/16 ,  H01L24/32 ,  H01L24/73 ,  H01L23/49816 ,  H01L21/4817 ,  H01L21/4853 ,  H01L24/81 ,  H01L2924/3025 ,  H01L2924/3511 ,  H01L2924/1431 ,  H01L2924/1432 ,  H01L2924/1436 ,  H01L2224/73253 ,  H01L2224/32245 ,  H01L2224/16225 ,  H01L2224/81097 ,  H01L2924/1616 ,  H01L2924/16235 ,  H01L2924/16251 ,  H01L2924/1632 ,  H01L2924/1659

Abstract: Electronic assemblies and methods of assembly are described. In an embodiment, an electronic assembly includes a stiffener structure shear bonded to an opposite side of a module substrate from a ball grid array (BGA) package. The stiffener structure may be shear bonded at elevated temperature after bonding of the BGA package to lock in a flat or near-flat surface contour of the module substrate.

公开(公告)号：US11646302B2

公开(公告)日：2023-05-09

申请号：US17013279

申请日：2020-09-04

Applicant: Apple Inc.

Inventor： Wei Chen ,  Jie-Hua Zhao ,  Jun Zhai ,  Po-Hao Chang ,  Hsien-Che Lin ,  Ying-Chieh Ke ,  Kunzhong Hu

IPC: H01L25/18 ,  H01L23/24

CPC classification number: H01L25/18 ,  H01L23/24

Abstract: Multiple chip module (MCM) structures are described. In an embodiment, a module includes a first and second components on the top side of a module substrate, a stiffener structure mounted on the top side of the module substrate, and a lid mounted on the stiffener structure and covering the first component and the second component. The stiffener is joined to the lid within a trench formed in a roof of the lid.

公开(公告)号：US20220231687A1

公开(公告)日：2022-07-21

申请号：US17678962

申请日：2022-02-23

Applicant: Apple Inc.

Inventor： Sanjay Dabral ,  Bahattin Kilic ,  Jie-Hua Zhao ,  Kunzhong Hu ,  Suk-Kyu Ryu

IPC: H03K19/1776 ,  G06F15/78 ,  H01L23/31 ,  H05K1/02

Abstract: Multi-chip systems and structures for modular scaling are described. In some embodiments an interfacing bar is utilized to couple adjacent chips. For example, a communication bar may utilized to coupled logic chips, and memory bar may be utilized to couple multiple memory chips to a logic chip.