摘要:
A method is provided for forming a metal silicide layer on a substrate. According to one embodiment the method includes providing the substrate in a process chamber, exposing the substrate at a first substrate temperature to a plasma generated from a deposition gas containing a metal precursor, where the plasma exposure forms a conformal metal-containing layer on the substrate in a self-limiting process. The method further includes exposing the metal-containing layer at a second substrate temperature to a reducing gas in the absence of a plasma, where the exposing steps are alternatively performed at least once to form the metal silicide layer, and the deposition gas does not contain the reducing gas. The method provides conformal metal silicide formation in deep trenches with high aspect ratios.
摘要:
A semiconducting device with a multilayer sidewall spacer and method of forming are described. In one embodiment, the method includes providing a substrate containing a patterned structure on a surface of the substrate and depositing a first spacer layer over the patterned structure at a first substrate temperature, where the first spacer layer contains a first material. The method further includes depositing a second spacer layer over the patterned substrate at a second substrate temperature that is different from the first substrate temperature, where the first and second materials contain the same chemical elements, and the depositing steps are performed in any order. The first and second spacer layers are then etched to form the multilayer sidewall spacer on the patterned structure.
摘要:
A method and system for monitoring status of a system component during a process. The method includes exposing a system component to a reactant gas during a process, where the reactant gas is capable of etching the system component material to form an erosion product, and monitoring release of the erosion product during the process to determine status of the system component. Processes that can be monitored include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, an injector, a substrate holder, a liner, a pedestal, a cap cover, an electrode, and a heater, any of which can further include a protective coating. The processing system includes the system component in a process chamber, a gas injection system for introducing the reactant gas, a chamber protection system for monitoring the status of the system component, and a controller for controlling the processing system in response to the status.
摘要:
A memory cell (101), its method of formation, and operation are disclosed. In accordance with one embodiment, the memory cell (101) comprises a first and second current carrying electrode (12) a control electrode (19), and doped discontinuous storage elements (17). In accordance with an alternative embodiment, memory cell programming is accomplished by removing or adding an average of approximately at least a first charge (30, 62, 64), which can be electron(s) or hole(s) from each of the doped discontinuous storage elements (17).
摘要:
A low temperature chemical vapor deposition process comprising heating in a chemical vapor depositon reactor a substrate upon which deposition is desired to a temperature of from about 550.degree. C. to about 750.degree. C. in a chemical vapor deposition reactor having a pressure of from about 0.1 torr to approximately atmospheric pressure, introducing into the reactor a silicon-containing feed and optionally an oxygen containing feed, said silicon containing feed consisting essentially of one or more compounds having the general formula ##STR1## wherein: R.sub.1, R.sub.2, R.sub.3 and R.sub.4 are hydrogen, azido or C-2 to C-6 alkyl, aryl or C-7 to C-10 aralkyl groups, at least one but not more than three of R.sub.1, R.sub.2, R.sub.3 and R.sub.4, being azido, and maintaining the temperature and pressure to cause a film of silicon nitride, silicon oxynitride or silicon dioxide to deposit is disclosed.
摘要:
A method of patterning a substrate. A sacrificial film is formed over a substrate and a pattern created therein. A first spacer layer is conformally deposited over the patterned sacrificial film and at least one horizontal portion of the first spacer layer is removed while vertical portions of the first spacer layer remain. A second spacer layer is conformally deposited over the patterned sacrificial film and the remaining portions of the first spacer layer. At least one horizontal portion of the second spacer layer is removed while vertical portions of the second spacer layer remain. Conformal deposition of the first and second spacer layers is optionally repeated one or more times. Conformal deposition of the first layer is optionally repeated. Then, one of the first or second spacer layers is removed while substantially leaving the vertical portions of the remaining one of the first or second spacer layers.
摘要:
A method and system are provided for monitoring status of a system component in a process chamber of a batch type processing system. The method includes exposing a system component to light from a light source and monitoring interaction of the light with the system component to determine status of the system component. The method can detect light transmission and/or light reflection from a system component during a process that can include a chamber cleaning process, a chamber conditioning process, a substrate etching process, and a substrate film formation process. The system component can be a consumable system part such as a process tube, a shield, a ring, a baffle, and a liner, and can further contain a protective coating.
摘要:
A semiconducting device with a dual sidewall spacer and method of forming are provided. The method includes: depositing a first spacer layer over a patterned structure, the first spacer layer having a seam propagating through a thickness of the first spacer layer near an interface region of a surface of the substrate and a sidewall of the patterned structure, etching the first spacer layer to form a residual spacer at the interface region, where the residual spacer coats less than the entirety of the sidewall of the patterned structure, depositing a second spacer layer on the residual spacer and on the sidewall of the patterned structure not coated by the residual spacer, the second spacer layer being seam-free on the seam of the residual spacer, and etching the second spacer layer to form a second spacer coating the residual spacer and coating the sidewall of the patterned structure not coated by the residual spacer.
摘要:
A method and control system for treating a hafnium-based dielectric processing system in which a system component of the processing system is exposed to a chlorine-containing gas. A residual hafnium by-product remaining in the processing system after a hafnium removal process is reacted with a chlorine-containing etchant derived from the chlorine-containing gas. A chlorinated hafnium product is volatilized for exhaustion from the processing system. The control system can utilize a computer readable medium to introduce a chlorine-containing gas to the processing system, to adjust at least one of a temperature and a pressure in the processing system to produce from the chlorine-containing gas a chlorine-containing etchant for dissolution of a residual hafnium by-product remaining in the processing system after a hafnium silicate, hafnium oxide, or hafnium oxynitride removal process, and to exhaust a chlorinated hafnium product from the processing system.
摘要:
A semiconductor device includes a memory array of static-random-access memory cells. The SRAM cells are formed using a process flow more closely associated with logic-type devices. The SRAM cells are formed using one semiconductor layer compared to at least three typically seen with SRAM cells. The SRAM cells include many features that allow its dimensions to be scaled to very small dimensions (less than 0.25 microns and possible down to 0.1 microns or even smaller). A unique process integration scheme allows formation of local interconnects (522 and 524), wherein each local interconnect (522, 524) cross couples the inverters of the SRAM and is formed within a single opening (70). Also, interconnect portions (104) of word lines are laterally offset from silicon portions (36) of the same word line, so that the interconnect portions do not interfere with bit line connections.