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公开(公告)号:US20140042621A1
公开(公告)日:2014-02-13
申请号:US13570065
申请日:2012-08-08
申请人: Chen-Hua Yu , Mirng-Ji Lii , Chien-Hsun Lee , Yung Ching Chen , Jiun Yi Wu
发明人: Chen-Hua Yu , Mirng-Ji Lii , Chien-Hsun Lee , Yung Ching Chen , Jiun Yi Wu
IPC分类号: H01L23/498 , H01L21/28 , H01L21/50
CPC分类号: H01L24/05 , H01L21/4853 , H01L23/49811 , H01L24/16 , H01L24/32 , H01L24/45 , H01L24/48 , H01L24/97 , H01L25/0657 , H01L25/105 , H01L25/50 , H01L2224/02166 , H01L2224/0401 , H01L2224/04042 , H01L2224/16238 , H01L2224/2919 , H01L2224/32145 , H01L2224/32225 , H01L2224/45015 , H01L2224/45124 , H01L2224/45144 , H01L2224/45147 , H01L2224/45164 , H01L2224/45169 , H01L2224/48091 , H01L2224/48227 , H01L2224/48463 , H01L2224/73204 , H01L2224/73215 , H01L2224/73265 , H01L2224/78301 , H01L2224/85045 , H01L2224/85375 , H01L2224/97 , H01L2225/1023 , H01L2225/1058 , H01L2924/00014 , H01L2924/15311 , H01L2924/15331 , H01L2924/181 , H01L2924/19107 , H01L2224/16225 , H01L2924/00 , H01L2924/0665 , H01L2924/00012 , H01L2924/2075 , H01L2924/20751
摘要: An embodiment is a package-on-package (PoP) device comprising a first package on a first substrate and a second package over the first package. A plurality of wire sticks disposed between the first package and the second package and the plurality of wire sticks couple the first package to the second package. Each of the plurality of wire sticks comprise a conductive wire of a first height affixed to a bond pad on the first substrate and each of the plurality of wire sticks is embedded in a solder joint.
摘要翻译: 一个实施例是一种封装封装(PoP)器件,其包括在第一衬底上的第一封装和在第一封装上的第二封装。 设置在第一封装和第二封装之间的多个线棒,并且多个线棒将第一封装耦合到第二封装。 多个线棒中的每一个包括固定到第一基板上的接合焊盘的第一高度的导线,并且多个线棒中的每一个嵌入焊接接头中。
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公开(公告)号:US20130277841A1
公开(公告)日:2013-10-24
申请号:US13452589
申请日:2012-04-20
申请人: Mirng-Ji Lii , Chen-Hua Yu , Chien-Hsiun Lee , Yung Ching Chen , Jiun Yi Wu
发明人: Mirng-Ji Lii , Chen-Hua Yu , Chien-Hsiun Lee , Yung Ching Chen , Jiun Yi Wu
CPC分类号: H01L23/49838 , H01L23/49811 , H01L23/5283 , H01L23/5386 , H01L24/13 , H01L24/16 , H01L24/20 , H01L24/24 , H01L25/105 , H01L2224/16238 , H01L2224/48091 , H01L2224/48227 , H01L2225/1023 , H01L2225/1058 , H01L2924/10253 , H01L2924/00014 , H01L2924/00
摘要: System and method are disclosed for creating a rigid interconnect between two substrate mounted packages to create a package-on-package assembly. A solid interconnect may have a predetermined length configured to provide a predetermined package separation, may be cylindrical, conical or stepped, may be formed by extrusion, casting, drawing or milling and may have an anti-oxidation coating. The interconnect may be attached to mounting pads on the top and bottom packages via an electrically conductive adhesive, including, but not limited to solder and solder paste. A solder preservative or other anti-oxidation coating may be applied to the mounting pad. A package-on-package assembly with solid interconnects may have a top package configured to accept at least one electronic device, with the solid interconnects mounted between the top package and a bottom package to rigidly hold the package about parallel to each other.
摘要翻译: 公开了用于在两个基板安装的封装之间创建刚性互连以产生封装封装组件的系统和方法。 固体互连可以具有预定长度,其被配置为提供预定的包装分离,可以是圆柱形,圆锥形或阶梯形,可以通过挤出,浇铸,拉拔或研磨形成,并且可以具有抗氧化涂层。 互连可以经由导电粘合剂附接到顶部和底部封装上的安装焊盘,包括但不限于焊料和焊膏。 可以将焊料防腐剂或其它抗氧化涂层施加到安装垫。 具有固体互连的封装封装组件可以具有被配置为接纳至少一个电子器件的顶部封装,其中固体互连件安装在顶部封装和底部封装之间,以使封装彼此平行地刚性地保持。
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公开(公告)号:US20060226549A1
公开(公告)日:2006-10-12
申请号:US11104266
申请日:2005-04-12
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L23/52 , H01L21/4763
CPC分类号: H01L21/76802 , H01L21/76807 , H01L21/76829 , H01L23/53238 , H01L23/5329 , H01L23/53295 , H01L2924/0002 , H01L2924/00
摘要: A semiconductor device and a fabrication method thereof. The semiconductor device has a substrate with a first conductive area, a dielectric layer formed of a low dielectric constant material disposed on the substrate, and a dielectric anti-reflective coating (DARC) layer disposed on the dielectric layer. A contact hole is disposed in the DARC layer and the dielectric layer to the first conductive area and a contact plug is disposed in the contact hole and electrically connected to the first conductive area.
摘要翻译: 半导体器件及其制造方法。 该半导体器件具有一个具有第一导电区域的基片,一个由布置在该基片上的低介电常数材料形成的电介质层,以及设置在介电层上的介电抗反射涂层(DARC)层。 接触孔设置在DARC层中,电介质层设置到第一导电区域,接触插头设置在接触孔中并电连接到第一导电区域。
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公开(公告)号:US08987085B2
公开(公告)日:2015-03-24
申请号:US11524000
申请日:2006-09-20
申请人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L21/768 , H01L21/02 , H01L21/3105
CPC分类号: H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译: 形成集成电路的方法包括提供半导体衬底,在半导体衬底上形成金属化层,其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层,对低k电介质层进行处理以形成亲水性顶表面,以及在溶液中的金属特征上镀覆盖层。
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公开(公告)号:US07629273B2
公开(公告)日:2009-12-08
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31 , H01L21/469
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US20090275195A1
公开(公告)日:2009-11-05
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
IPC分类号: H01L21/768
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US20080085607A1
公开(公告)日:2008-04-10
申请号:US11523674
申请日:2006-09-19
申请人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
发明人: Chen-Hua Yu , Hung Chun Tsai , Hui-Lin Chang , Ting-Yu Shen , Yung-Cheng Lu
IPC分类号: H01L21/31
CPC分类号: H01L21/3105 , H01L21/823807 , H01L29/7843
摘要: A method for forming a semiconductor structure includes providing a substrate comprising a first device region, forming a metal-oxide-semiconductor (MOS) device in the first device region, forming a stressed layer over the MOS device, and performing a post-treatment to modulate a stress of the stressed layer. The post-treatment is selected from the group consisting essentially of ultra-violet (UV) curing, laser curing, e-Beam curing, and combinations thereof.
摘要翻译: 一种形成半导体结构的方法包括提供包括第一器件区域的衬底,在第一器件区域中形成金属氧化物半导体(MOS)器件,在MOS器件上形成应力层,并进行后处理 调节应力层的应力。 后处理选自基本上由紫外线(UV)固化,激光固化,电子束固化及其组合组成的组。
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公开(公告)号:US20080032472A1
公开(公告)日:2008-02-07
申请号:US11524000
申请日:2006-09-20
申请人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Ming-Shih Yeh , Chih-Hsien Lin , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L21/8242
CPC分类号: H01L21/76849 , H01L21/02074 , H01L21/3105 , H01L21/76826
摘要: A method of forming an integrated circuit includes providing a semiconductor substrate, forming a metallization layer over the semiconductor substrate, wherein the metallization layer comprises a metal feature in a low-k dielectric layer and extending from a top surface of the low-k dielectric layer into the low-k dielectric layer, performing a treatment to the low-k dielectric layer to form a hydrophilic top surface, and plating a cap layer on the metal feature in a solution.
摘要翻译: 形成集成电路的方法包括提供半导体衬底,在半导体衬底上形成金属化层,其中金属化层包括低k电介质层中的金属特征并且从低k电介质层的顶表面延伸 进入低k电介质层,对低k电介质层进行处理以形成亲水性顶表面,以及在溶液中的金属特征上镀覆盖层。
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公开(公告)号:US08143162B2
公开(公告)日:2012-03-27
申请号:US12500796
申请日:2009-07-10
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang , Ting-Yu Shen , Hung Chun Tsai
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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公开(公告)号:US20070228571A1
公开(公告)日:2007-10-04
申请号:US11523940
申请日:2006-09-20
申请人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
发明人: Chen-Hua Yu , Yung-Cheng Lu , Hui-Lin Chang
IPC分类号: H01L23/52
CPC分类号: H01L23/53238 , H01L21/76826 , H01L21/76829 , H01L21/76834 , H01L21/76849 , H01L21/76856 , H01L21/76864 , H01L23/5329 , H01L2924/0002 , H01L2924/00
摘要: An interconnect structure of an integrated circuit and a method for forming the same are provided. The interconnect structure includes a semiconductor substrate, a low-k dielectric layer over the semiconductor substrate, a conductor in the low-k dielectric layer, and a cap layer on the conductor. The cap layer has at least a top portion comprising a metal silicide/germanide.
摘要翻译: 提供集成电路的互连结构及其形成方法。 互连结构包括半导体衬底,半导体衬底上的低k电介质层,低k电介质层中的导体和导体上的覆盖层。 盖层至少具有包含金属硅化物/锗化物的顶部。
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