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    Circuit board and manufacturing method thereof
    12.
    发明授权
    Circuit board and manufacturing method thereof 有权
    电路板及其制造方法

    公开(公告)号：US08294041B2

    公开(公告)日：2012-10-23

    申请号：US12170082

    申请日：2008-07-09

    Applicant: Cheng-Po Yu ,  Cheng-Hung Yu

    Inventor： Cheng-Po Yu ,  Cheng-Hung Yu

    IPC: H05K1/11

    CPC classification number: H05K1/0231 ,  H05K1/0219 ,  H05K1/162 ,  H05K3/107 ,  H05K2201/09036 ,  H05K2201/09809 ,  Y10T29/49117

    Abstract: A circuit board including a first dielectric layer having a first surface and a second surface, a first circuit layer, a second dielectric layer, and a second circuit layer is provided. At least one trench is formed on the first surface, and the first circuit layer is formed on an inside wall of the trench. In addition, the second dielectric layer is disposed in the trench, and covers the first circuit layer. The second circuit layer is disposed in the trench, and the second dielectric layer is located between the first circuit layer and the second circuit layer. A manufacturing method of the circuit board is further provided.

    Abstract translation: 提供一种电路板，包括具有第一表面和第二表面的第一介电层，第一电路层，第二电介质层和第二电路层。 在第一表面上形成至少一个沟槽，并且第一电路层形成在沟槽的内壁上。 此外，第二电介质层设置在沟槽中并覆盖第一电路层。 第二电路层设置在沟槽中，第二电介质层位于第一电路层和第二电路层之间。 还提供了电路板的制造方法。

    EMBEDDED WIRING BOARD AND A MANUFACTURING METHOD THEREOF
    13.
    发明申请
    EMBEDDED WIRING BOARD AND A MANUFACTURING METHOD THEREOF 有权
    嵌入式接线板及其制造方法

    公开(公告)号：US20120231179A1

    公开(公告)日：2012-09-13

    申请号：US13474735

    申请日：2012-05-18

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/00 ,  C25D5/02 ,  B05D3/06

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: An embedded wiring board includes an upper wiring layer, a lower wiring layer, an insulation layer, a first conductive pillar and a second conductive pillar. The upper wiring layer contains an upper pad, the lower wiring layer contains a lower pad, and the insulation layer contains an upper surface and a lower surface opposite to the upper surface. The upper pad is embedded in the upper surface and the lower pad is embedded in the lower surface. The first conductive pillar is located in the insulation layer and includes an end surface which is exposed by the upper surface. A height of the first conductive pillar relative to the upper surface is larger than a depth of the upper pad relative to the upper surface. In addition, the second conductive pillar is located in the insulation layer and is connected between the first conductive pillar and the lower pad.

    Abstract translation: 嵌入布线板包括上布线层，下布线层，绝缘层，第一导电柱和第二导电柱。 上布线层包含上焊盘，下布线层包含下焊盘，绝缘层包含与上表面相对的上表面和下表面。 上垫片嵌入在上表面中，下垫片嵌入下表面。 第一导电柱位于绝缘层中，并且包括由上表面暴露的端面。 第一导电柱相对于上表面的高度大于上垫相对于上表面的深度。 此外，第二导电柱位于绝缘层中并连接在第一导电柱和下垫之间。

    CIRCUIT STRUCTURE OF CIRCUIT BOARD
    14.
    发明申请
    CIRCUIT STRUCTURE OF CIRCUIT BOARD 有权
    电路板电路结构

    公开(公告)号：US20120067630A1

    公开(公告)日：2012-03-22

    申请号：US13305310

    申请日：2011-11-28

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/09 ,  H05K1/00

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    Process of fabricating circuit structure
    15.
    发明授权
    Process of fabricating circuit structure 有权
    制作电路结构的过程

    公开(公告)号：US07921550B2

    公开(公告)日：2011-04-12

    申请号：US12345474

    申请日：2008-12-29

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/00

    CPC classification number: H05K1/116 ,  H01L21/6835 ,  H01L2221/68359 ,  H05K3/20 ,  H05K3/4644 ,  H05K3/4658 ,  H05K2201/09454 ,  H05K2201/09563 ,  H05K2201/096 ,  Y10T29/49124

    Abstract: A process for forming a circuit structure includes providing a first composite-layer structure at first. A second composite-layer structure is then provided. The first composite-layer structure, a second dielectric layer and the second composite-layer structure are pressed so that a second circuit pattern and an independent via pad are embedded in the second dielectric layer, and the second dielectric layer is connected to the first dielectric layer. A first carrier substrate and a second carrier substrate are removed to expose a first circuit pattern and the second circuit pattern. At least one first opening that passes through the second dielectric layer and exposes the independent via pad is formed, and the first opening is filled with a conductive material to form a second conductive via that connects the independent via pad and a second via pad.

    Abstract translation: 一种形成电路结构的工艺包括首先提供第一复合层结构。 然后提供第二复合层结构。 第一复合层结构，第二介电层和第二复合层结构被按压，使得第二电路图案和独立通孔焊盘嵌入第二电介质层中，并且第二电介质层连接到第一电介质层 层。 去除第一载体衬底和第二载体衬底以暴露第一电路图案和第二电路图案。 形成穿过第二电介质层并暴露独立通孔焊盘的至少一个第一开口，并且用导电材料填充第一开口以形成连接独立通孔焊盘和第二通孔焊盘的第二导电通孔。

    CIRCUIT STRUCTURE OF CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME
    17.
    发明申请
    CIRCUIT STRUCTURE OF CIRCUIT BOARD AND PROCESS FOR MANUFACTURING THE SAME 有权
    电路板的电路结构及其制造工艺

    公开(公告)号：US20100059256A1

    公开(公告)日：2010-03-11

    申请号：US12270718

    申请日：2008-11-13

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K1/09 ,  H05K1/00 ,  H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/0265 ,  H05K3/0032 ,  H05K3/06 ,  H05K3/061 ,  H05K2201/0376 ,  H05K2201/09727 ,  H05K2203/0369 ,  Y10T29/49117 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49165

    Abstract: A circuit structure of a circuit board includes a dielectric layer, a number of first circuits, and a number of second circuits. The dielectric layer has a surface and an intaglio pattern. The first circuits are disposed on the surface of the dielectric layer. The second circuits are disposed in the intaglio pattern of the dielectric layer. Line widths of the second circuits are smaller than line widths of the first circuits, and a distance between every two of the adjacent second circuits is shorter than a distance between every two of the adjacent first circuits.

    Abstract translation: 电路板的电路结构包括电介质层，多个第一电路和多个第二电路。 电介质层具有表面和凹版图案。 第一电路设置在电介质层的表面上。 第二电路设置在电介质层的凹版图案中。 第二电路的线宽小于第一电路的线宽，并且相邻的第二电路中的每两个之间的距离比相邻的第一电路中的每两个之间的距离短。

    Method of forming solder mask and wiring board with solder mask
    18.
    发明授权
    Method of forming solder mask and wiring board with solder mask 有权
    用焊接掩模形成焊锡掩模和接线板的方法

    公开(公告)号：US07520755B2

    公开(公告)日：2009-04-21

    申请号：US11307425

    申请日：2006-02-07

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

    IPC: H01R12/00

    CPC classification number: H05K3/28 ,  H05K3/3452 ,  H05K2203/013 ,  H05K2203/0557 ,  H05K2203/058 ,  H05K2203/1476

    Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

    Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。

    Method of manufacturing embedded wiring board
    19.
    发明授权
    Method of manufacturing embedded wiring board 有权
    嵌入式布线板的制造方法

    公开(公告)号：US09210815B2

    公开(公告)日：2015-12-08

    申请号：US13474735

    申请日：2012-05-18

    Applicant: Cheng-Po Yu

    Inventor： Cheng-Po Yu

    IPC: H05K3/36 ,  H05K3/00 ,  H05K3/46 ,  H05K3/10

    CPC classification number: H05K3/0035 ,  H05K3/107 ,  H05K3/465 ,  H05K2201/0236 ,  H05K2201/0959 ,  H05K2201/09845 ,  H05K2203/1476 ,  Y10T29/49155

    Abstract: A manufacturing method of an embedded wiring board is provided. The method includes the following steps. First, an insulation layer and a lower wiring layer are provided, wherein the insulation layer includes a polymeric material. Then, the plural catalyst grains are distributed in the polymeric material. A groove and an engraved pattern are formed on the upper surface. A blind via is formed on a bottom surface of the groove to expose the lower pad. An upper wiring layer is formed in the engraved pattern. Some catalyst grains are exposed and activated in the groove, the engraved pattern and the blind via. A first conductive pillar is formed in the groove. Finally, a second conductive pillar is formed in the blind via.

    Abstract translation: 提供了一种嵌入式布线板的制造方法。 该方法包括以下步骤。 首先，提供绝缘层和下布线层，其中绝缘层包括聚合材料。 然后，多个催化剂颗粒分布在聚合物材料中。 在上表面上形成有凹槽和雕刻图案。 在槽的底表面上形成盲孔以露出下垫。 上部布线层形成在雕刻图案中。 一些催化剂颗粒在凹槽，雕刻图案和盲孔中暴露和活化。 第一导电柱形成在凹槽中。 最后，在盲通孔中形成第二导电柱。

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