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    CIRCUIT BOARD
    2.
    发明申请
    CIRCUIT BOARD 审中-公开
    电路板

    公开(公告)号：US20120031651A1

    公开(公告)日：2012-02-09

    申请号：US12944275

    申请日：2010-11-11

    Applicant: TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： TZYY-JANG TSENG ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/02 ,  H05K1/18

    CPC classification number: H05K1/0203 ,  H05K1/056 ,  H05K3/3436 ,  H05K2201/0187 ,  H05K2201/10106

    Abstract: A circuit board including a circuit layer, a thermally conductive substrate, an insulation layer, and at least one thermally conductive material is provided. The thermally conductive substrate has a plane. The insulation layer is disposed between the circuit layer and the plane and partially covers the plane. The thermally conductive material covers the plane without covered by the insulation layer and is in contact with the thermally conductive substrate. The insulation layer exposes the thermally conductive material.

    Abstract translation: 提供了包括电路层，导热基板，绝缘层和至少一种导热材料的电路板。 导热基板具有平面。 绝缘层设置在电路层和平面之间，并部分覆盖平面。 导热材料覆盖该平面而不被绝缘层覆盖，并与导热基板接触。 绝缘层暴露导热材料。

    Method of fabricating substrate
    3.
    发明授权
    Method of fabricating substrate 有权
    制造基板的方法

    公开(公告)号：US07867908B2

    公开(公告)日：2011-01-11

    申请号：US12422428

    申请日：2009-04-13

    Applicant: Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    Inventor： Tzyy-Jang Tseng ,  Chih-Ming Chang ,  Cheng-Po Yu ,  Chung W. Ho

    IPC: H01L21/302

    CPC classification number: H01L23/142 ,  H01L21/6835 ,  H01L33/486 ,  H01L33/62 ,  H01L33/642 ,  H01L2224/32245 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/181 ,  H05K3/06 ,  H05K3/202 ,  H05K2201/09881 ,  H05K2203/0369 ,  H05K2203/1476 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014

    Abstract: A method of fabricating a substrate includes following steps. First, a metallic panel having a first surface and a second surface is provided. A first half-etching process is carried out to etch the first surface of the metallic panel to a first depth so that a first patterned metallic layer is formed on the first surface. Next, a first insulating material is deposited into gaps in the first patterned metallic layer to form a first insulator. Thereafter, a second half-etching process is carried out to etch the second surface of the metallic panel to a second depth and expose at least a portion of the first insulator so that a second patterned metallic layer is formed on the second surface. The first depth and the second depth together equal the thickness of the metallic panel.

    Abstract translation: 制造衬底的方法包括以下步骤。 首先，提供具有第一表面和第二表面的金属板。 执行第一半蚀刻工艺以将金属板的第一表面蚀刻到第一深度，使得在第一表面上形成第一图案化金属层。 接下来，将第一绝缘材料沉积在第一图案化金属层中的间隙中以形成第一绝缘体。 此后，执行第二半蚀刻工艺以将金属板的第二表面蚀刻到第二深度并且暴露第一绝缘体的至少一部分，使得在第二表面上形成第二图案化金属层。 第一深度和第二深度一起等于金属面板的厚度。

    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL
    5.
    发明申请
    METHOD FOR FORMING CIRCUIT BOARD STRUCTURE OF COMPOSITE MATERIAL 审中-公开
    形成复合材料电路板结构的方法

    公开(公告)号：US20100266752A1

    公开(公告)日：2010-10-21

    申请号：US12763224

    申请日：2010-04-20

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu ,  Wen-Fang Liu

    IPC: H05K3/10

    CPC classification number: H05K3/107 ,  H05K1/036 ,  H05K1/0373 ,  H05K3/181 ,  H05K3/184 ,  H05K3/185 ,  H05K2201/0236 ,  H05K2201/0257 ,  H05K2203/0264 ,  H05K2203/107 ,  H05K2203/308

    Abstract: A method for forming a circuit board structure of composite material is disclosed. First, a composite material structure including a substrate and a composite material dielectric layer is provided. The composite material dielectric layer includes a catalyst dielectric layer contacting the substrate and at least one sacrificial layer contacting the catalyst dielectric layer. The sacrificial layer is insoluble in water. Later, the composite material dielectric layer is patterned and simultaneously catalyst particles are activated. Then, a conductive layer is formed on the activated catalyst particles. Afterwards, at least one sacrificial layer is removed.

    Abstract translation: 公开了一种形成复合材料的电路板结构的方法。 首先，提供包括基板和复合材料介电层的复合材料结构。 复合材料介电层包括与基底接触的催化剂介电层和与催化剂介电层接触的至少一个牺牲层。 牺牲层不溶于水。 之后，复合材料介电层被图案化，同时催化剂颗粒被激活。 然后，在活化的催化剂颗粒上形成导电层。 之后，去除至少一个牺牲层。

    Method of forming solder mask and wiring board with solder mask
    7.
    发明授权
    Method of forming solder mask and wiring board with solder mask 有权
    用焊接掩模形成焊锡掩模和接线板的方法

    公开(公告)号：US07520755B2

    公开(公告)日：2009-04-21

    申请号：US11307425

    申请日：2006-02-07

    Applicant: Tzyy-Jang Tseng ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Cheng-Po Yu

    IPC: H01R12/00

    CPC classification number: H05K3/28 ,  H05K3/3452 ,  H05K2203/013 ,  H05K2203/0557 ,  H05K2203/058 ,  H05K2203/1476

    Abstract: A method of forming solder mask, suitable for forming a solder mask on the surface of a wiring board, is provided. The surface of the wiring board includes a first region and a second region, and the surface of the wiring board has a wiring pattern thereon. The method includes forming a first sub solder mask in the first region on the surface of the wiring board by performing a screen-printing or a photolithographic process, and forming a second sub solder mask in the second region on the surface of the wiring board by performing an ink-jet printing process. The method not only improves the precision of the solder mask alignment on the wiring board and its reliability, but also increases the production rate and lowers the manufacturing cost.

    Abstract translation: 提供一种形成焊接掩模的方法，该方法适用于在布线板的表面上形成焊接掩模。 布线板的表面包括第一区域和第二区域，并且布线板的表面上具有布线图案。 该方法包括通过丝网印刷或光刻工艺在布线板的表面上的第一区域中形成第一子焊料掩模，并且在布线板的表面上的第二区域中形成第二副焊料掩模 进行喷墨打印处理。 该方法不仅提高了布线板上的焊盘对准的精度及其可靠性，而且提高了生产率，降低了制造成本。

    Circuit structure
    8.
    发明授权
    Circuit structure 有权
    电路结构

    公开(公告)号：US08288662B2

    公开(公告)日：2012-10-16

    申请号：US12718194

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/184 ,  H05K3/0032 ,  H05K3/387 ,  H05K3/421 ,  H05K3/465 ,  H05K3/4661 ,  H05K2201/0195 ,  H05K2201/0347 ,  H05K2203/107 ,  H05K2203/1173

    Abstract: A circuit structure including a circuit board, an insulating layer, a conductive via, a platable dielectric layer and a conductive pattern is provided. The insulating layer is disposed on the circuit board and covers a circuit layer of the circuit board. The conductive via passes through the insulating layer and connects the circuit layer and protrudes from a surface of the insulating layer. The platable dielectric layer having a trench pattern is disposed on the surface of the insulating layer wherein the portion of the conductive via protruding from the surface is located in the trench pattern. The material of the platable dielectric layer includes a chemical platable material. The conductive pattern is in the trench pattern and connects the conductive via wherein an interface exists between the conductive pattern and the conductive via and protrudes from the surface of the insulating layer.

    Abstract translation: 提供了包括电路板，绝缘层，导电通孔，可镀介电层和导电图案的电路结构。 绝缘层设置在电路板上并覆盖电路板的电路层。 导电通孔穿过绝缘层并连接电路层并从绝缘层的表面突出。 具有沟槽图案的可镀介电层设置在绝缘层的表面上，其中从表面突出的导电通孔的部分位于沟槽图案中。 可镀介电层的材料包括化学镀层材料。 导电图案处于沟槽图案中并且连接导电通孔，其中在导电图案和导电通孔之间存在界面，并从绝缘层的表面突出。

    Circuit substrate and manufacturing method thereof
    9.
    发明授权
    Circuit substrate and manufacturing method thereof 有权
    电路基板及其制造方法

    公开(公告)号：US08247705B2

    公开(公告)日：2012-08-21

    申请号：US12718226

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/11

    CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

    Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

    CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF
    10.
    发明申请
    CIRCUIT SUBSTRATE AND MANUFACTURING METHOD THEREOF 有权
    电路基板及其制造方法

    公开(公告)号：US20110155427A1

    公开(公告)日：2011-06-30

    申请号：US12718226

    申请日：2010-03-05

    Applicant: Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    Inventor： Tzyy-Jang Tseng ,  Chang-Ming Lee ,  Wen-Fang Liu ,  Cheng-Po Yu

    IPC: H05K1/09 ,  B05D5/12 ,  H05K1/11 ,  H05K1/02

    CPC classification number: H05K3/387 ,  C23C18/1653 ,  H05K3/4644 ,  H05K2201/0129 ,  H05K2201/0145 ,  H05K2201/0154 ,  Y10T29/49126 ,  Y10T29/49155 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T428/24322

    Abstract: A manufacturing method of a circuit substrate includes the following steps. A dielectric layer is formed on at least one surface of a substrate. An insulating layer is formed on the dielectric layer. A portion of the insulating layer and a portion of the dielectric layer are removed, so as to form at least one blind via in the dielectric layer and the insulating layer. An electroless plating layer is formed on the sidewall of the blind via and a remaining portion of the insulating layer, wherein the binding strength between the insulating layer and the electroless plating layer is greater than that between the dielectric layer and the electroless plating layer. A patterned conductive layer is plated to cover the electroless plating layer.

    Abstract translation: 电路基板的制造方法包括以下步骤。 在基板的至少一个表面上形成介电层。 在电介质层上形成绝缘层。 去除绝缘层的一部分和电介质层的一部分，以在电介质层和绝缘层中形成至少一个盲孔。 在盲通孔的侧壁和绝缘层的剩余部分上形成化学镀层，其中绝缘层和化学镀层之间的结合强度大于介电层和化学镀层之间的结合强度。 电镀图案化导电层以覆盖化学镀层。

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