公开(公告)号：US5717238A

公开(公告)日：1998-02-10

申请号：US677078

申请日：1996-07-09

Applicant: Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

Inventor： Sheldon Aronowitz ,  James Kimball ,  Yu-Lam Ho ,  Gobi Padmanabhan ,  Douglas T. Grider ,  Chi-Yi Kao

IPC: H01L21/265 ,  H01L21/336 ,  H01L29/76 ,  H01L29/94

CPC classification number: H01L29/6659 ,  H01L21/26506

Abstract: A process and resulting product are described for controlling the channeling and/or diffusion of a boron dopant in a P- region forming the lightly doped drain (LDD) region of a PMOS device in a single crystal semiconductor substrate, such as a silicon substrate. The channeling and/or diffusion of the boron dopant is controlled by implanting the region, prior to implantation with a boron dopant, with noble gas ions, such as argon ions, at a dosage at least equal to the subsequent dosage of the implanted boron dopant, but not exceeding an amount equivalent to the implantation of about 3.times.10.sup.14 argon ions/cm.sup.2 into a silicon substrate, whereby channeling and diffusion of the subsequently implanted boron dopant is inhibited without, however, amorphizing the semiconductor substrate.

Abstract translation: 描述了一种工艺和产生的产品，用于控制在诸如硅衬底的单晶半导体衬底中形成PMOS器件的轻掺杂漏极（LDD）区域的P区中的硼掺杂剂的沟道化和/或扩散。 硼掺杂剂的通道和/或扩散通过在用硼掺杂剂注入之前用惰性气体离子（例如氩离子）注入该区域，剂量至少等于注入的硼掺杂剂的后续剂量 但不超过等于将约3×1014个氩离子/ cm 2注入到硅衬底中的量的量，由此抑制随后注入的硼掺杂剂的引导和扩散，而不会使半导体衬底非晶化。

公开(公告)号：US5508211A

公开(公告)日：1996-04-16

申请号：US198911

申请日：1994-02-17

Applicant: Abraham Yee ,  Sheldon Aronowitz

Inventor： Abraham Yee ,  Sheldon Aronowitz

IPC: H01L21/265 ,  H01L21/762

CPC classification number: H01L21/26533 ,  H01L21/26506 ,  H01L21/76264 ,  H01L21/76267 ,  H01L21/76281 ,  H01L21/76283

Abstract: An integrated circuit structure vertically isolated electrically from the underlying substrate is formed in/on a single crystal semiconductor substrate, such as a silicon semiconductor wafer, by first implanting the substrate with a sufficient dosage of noble gas atoms to inhibit subsequent recrystallization of the semiconductor lattice in the implanted region during subsequent annealing, resulting in the formation of an isolation layer comprising implanted noble gas atoms enmeshed with semiconductor atoms in the substrate which has sufficient resistivity to act as an isolation layer. The preferred noble gases used to form such isolation layers are neon, argon, krypton, and xenon. When neon atoms are implanted, the minimum dosage should be at least about 6.times.10.sup.15 neon atoms/cm.sup.2 to inhibit subsequent recrystallization of the silicon substrate. When argon atoms are implanted, the minimum dosage should be at least about 2.times.10.sup.15 argon atoms/cm.sup.2. When krypton is implanted, the minimum dosage should be at least about 6.times.10.sup.24 krypton atoms/cm.sup.2. The energy used for the implant should be sufficient to provide an average implant depth sufficient to form, after annealing, the noble gas isolation layer at a depth of at least about 0.5 microns from the surface.

Abstract translation: 通过首先用足够量的惰性气体原子注入衬底以抑制随后的半导体晶格的再结晶，在诸如硅半导体晶片的单晶半导体衬底中/之上形成与下面的衬底电垂直隔离的集成电路结构 在随后退火期间的注入区域中，导致形成隔离层，该隔离层包含与衬底中具有充分电阻率充当隔离层的半导体原子嵌入的惰性气体原子。 用于形成这种隔离层的优选稀有气体是氖，氩，氪和氙。 当植入氖原子时，最小剂量应为至少约6×10 15氖原子/ cm 2以抑制随后的硅衬底的再结晶。 当注入氩原子时，最小剂量应至少为约2×1015氩原子/ cm2。 当植入氪时，最小剂量应为至少约6×1024氪原子/ cm2。 用于植入物的能量应足以提供足够的平均植入深度，以在退火之后形成距离表面至少约0.5微米深度的惰性气体隔离层。

公开(公告)号：US5376560A

公开(公告)日：1994-12-27

申请号：US186201

申请日：1994-01-24

Applicant: Sheldon Aronowitz ,  Courtney L. Hart

Inventor： Sheldon Aronowitz ,  Courtney L. Hart

IPC: H01L21/322 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/3226 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76283 ,  Y10S438/966

Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide. The remaining open space of the second trenches is filled, and devices of any desired type are formed in the single crystal islands.

公开(公告)号：US5372952A

公开(公告)日：1994-12-13

申请号：US863651

申请日：1992-04-03

Applicant: Sheldon Aronowitz ,  Courtney L. Hart

Inventor： Sheldon Aronowitz ,  Courtney L. Hart

IPC: H01L21/322 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/3226 ,  H01L21/76202 ,  H01L21/76264 ,  H01L21/7627 ,  H01L21/76283 ,  Y10S438/966

Abstract: A number of dielectrically isolated single crystal islands are formed by implanting neon or other group Zero ions into a semiconductor substrate, preferably silicon, at a sufficiently high energy to created an amorphized region in the interior of the substrate, without excessively damaging the substrate surface through which the ions pass. The amorphized regions are highly resistive, and are suitable for isolation in some applications. Where better isolation is desired, a dielectric isolation structure is formed as follows. Trenches are formed down into the amorphized regions, and the substrate is heavily oxidized to convert the amorphized regions into buried oxide regions and the island sidewalls into oxide. The islands are made thicker by removing the oxide from the islands' top surfaces and sidewalls, and growing epitaxial silicon over the substrate. Second trenches are formed down to the buried oxide regions, and the substrate is again oxidized to convert the islands' sidewalls to oxide. The remaining open space of the second trenches is filled, and devices of any desired type are formed in the single crystal islands.

Abstract translation: 通过以足够高的能量将氖或其它基团零离子注入到半导体衬底（优选硅）中来形成多个介电隔离的单晶岛，以在衬底的内部产生非晶化区域，而不会过度损坏衬底表面 离子通过。 非晶化区域是高电阻性的，并且在一些应用中适合于隔离。 在需要更好的隔离的情况下，如下形成绝缘隔离结构。 沟槽形成为非晶化区域，并且衬底被高度氧化，以将非晶化区域转变为掩埋氧化物区域，并将岛侧壁变成氧化物。 通过从岛的顶表面和侧壁去除氧化物并在衬底上生长外延硅，使得岛变得更厚。 第二沟槽形成到埋置的氧化物区域，并且衬底再次被氧化以将岛的侧壁转变为氧化物。 填充第二沟槽的剩余开放空间，并且在单晶岛中形成任何所需类型的装置。

公开(公告)号：US5280185A

公开(公告)日：1994-01-18

申请号：US738798

申请日：1991-07-31

Applicant: Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

Inventor： Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L29/161 ,  H01L31/117 ,  H01L29/167 ,  H01L29/207 ,  H01L29/227

CPC classification number: H01L29/161 ,  H01L21/22 ,  H01L21/26506

Abstract: A structure of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

Abstract translation: 提供了使用锗抑制硅中的掺杂剂扩散的结构。 锗分布在硅晶格中的取代位置，以形成两个锗区域，这两个区域插入在要引入掺杂剂的区域和掺杂剂被排除的区域之间，两个锗区域充当掺杂剂扩散势垒。

公开(公告)号：US5095358A

公开(公告)日：1992-03-10

申请号：US510742

申请日：1990-04-18

Applicant: Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

Inventor： Sheldon Aronowitz ,  Courtney L. Hart ,  Sung T. Ahn

IPC: H01L21/22 ,  H01L21/225 ,  H01L21/265 ,  H01L29/161

CPC classification number: H01L29/161 ,  H01L21/22 ,  H01L21/26506

Abstract: A method of inhibiting dopant diffusion in silicon using germanium is provided. Germanium is distributed in substitutional sites in a silicon lattice to form two regions of germanium interposed between a region where dopant is to be introduced and a region from which dopant is to be excluded, the two germanium regions acting as a dopant diffusion barrier.

公开(公告)号：US20050179138A1

公开(公告)日：2005-08-18

申请号：US11104763

申请日：2005-04-12

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: H01L21/44 ,  H01L21/768 ,  H01L29/40

CPC classification number: H01L21/76831 ,  H01L21/76802

Abstract: A barrier layer for a semiconductor device is provided. The semiconductor device comprises a dielectric layer, an electrically conductive copper containing layer, and a barrier layer separating the dielectric layer from the copper containing layer. The barrier layer comprises a silicon oxide layer and a dopant, where the dopant is a divalent ion, which dopes the silicon oxide layer adjacent to the copper containing layer. A method of forming a barrier layer is provided. A silicon oxide layer with a surface is provided. The surface of the silicon oxide layer is doped with a divalent ion to form a barrier layer extending to the surface of the silicon oxide layer. An electrically conductive copper containing layer is formed on the surface of the barrier layer, where the barrier layer prevents diffusion of copper into the substrate.

Abstract translation: 提供了一种用于半导体器件的阻挡层。 该半导体器件包括电介质层，导电含铜层和将电介质层与含铜层隔开的阻挡层。 阻挡层包括氧化硅层和掺杂剂，其中掺杂剂是二价离子，其掺杂与含铜层相邻的氧化硅层。 提供形成阻挡层的方法。 提供具有表面的氧化硅层。 氧化硅层的表面掺杂有二价离子以形成延伸到氧化硅层的表面的势垒层。 在阻挡层的表面上形成导电含铜层，其中阻挡层防止铜扩散到衬底中。

公开(公告)号：US06897102B2

公开(公告)日：2005-05-24

申请号：US10313333

申请日：2002-12-06

Applicant: Sheldon Aronowitz ,  Mohammed Mirabedini

Inventor： Sheldon Aronowitz ,  Mohammed Mirabedini

IPC: H01L21/28 ,  H01L21/336 ,  H01L21/84 ,  H01L29/51 ,  H01L31/113

CPC classification number: H01L21/28194 ,  H01L21/28176 ,  H01L29/513 ,  H01L29/517

Abstract: A method of preparing a polysilicon gate to minimize gate depletion and dopant penetration and to increase conductivity is revealed. Several monolayers of atomic are condensed onto a gate dielectric. Polysilicon is deposited onto the calcium and patterned in a standard way. The exposed calcium is then removed by raising the temperature to approximately 600° C. The calcium remaining between the gate dielectric and the polysilicon blocks channeling of dopant to minimize depletion and penetration, increase conductivity, and allow for longer and higher-temperature annealing.

Abstract translation: 揭示了制备多晶硅栅极以最小化栅极耗尽和掺杂剂穿透并增加电导率的方法。 几个原子的单层会凝结在栅极电介质上。 多晶硅沉积在钙上并以标准方式图案化。 然后通过将温度升高至约600℃来除去暴露的钙。残留在栅极电介质和多晶硅之间的钙阻挡掺杂剂的通道，以使耗尽和穿透最小化，增加导电性，并允许更长时间和更高温退火。

公开(公告)号：US20050098856A1

公开(公告)日：2005-05-12

申请号：US10652007

申请日：2003-08-29

Applicant: Sheldon Aronowitz ,  Vladimir Zubkov

Inventor： Sheldon Aronowitz ,  Vladimir Zubkov

IPC: C01B33/12 ,  C23C16/40 ,  H01L21/312 ,  H01L21/314 ,  H01L21/316 ,  H01L21/31 ,  H01L23/58

CPC classification number: H01L21/02126 ,  C01B33/126 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/3121 ,  H01L21/31629 ,  H01L21/31633 ,  Y02P20/129

Abstract: The invention provides a process for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes containing one or more organofluoro silanes having the formula SiR1R2R3R4, where: (a) R1 is selected from H, a 3 to 10 carbon alkyl, and an alkoxy; (b) R2 contains at least one C atom bonded to at least one F atom, and no aliphatic C—H bonds; and (c) R3 and R4 are selected from H, alkyl, alkoxy, a moiety containing at least one C atom bonded to at least one F atom, and ((L)Si(R5)(R6))n(R7); where n ranges from 1 to 10; L is O or CFR8; each n R5 and R6 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; R7 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom; and each R8 is selected from H, alkyl, alkoxy, and a moiety containing at least one C atom bonded to at least one F atom. Also provided is a low dielectric constant fluorine and carbon-doped silicon oxide dielectric material for use in an integrated circuit structure which contains: silicon atoms bonded to oxygen atoms; silicon atoms bonded to carbon atoms; and carbon atoms bonded to fluorine atoms; where the dielectric material also has a characteristic selected from: (a) the presence of at least one C—C bond; (b) the presence of at least one carbon atom bonded to from 1 to 2 fluorine atoms; and (c) the presence of at least one silicon atom bonded to from 0 to 2 oxygen atoms.

公开(公告)号：US06572925B2

公开(公告)日：2003-06-03

申请号：US09792683

申请日：2001-02-23

Applicant: Vladimir Zubkov ,  Sheldon Aronowitz

Inventor： Vladimir Zubkov ,  Sheldon Aronowitz

IPC: C23C1640

CPC classification number: H01L21/02131 ,  C23C16/401 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/3122 ,  H01L21/3127 ,  H01L21/31629

Abstract: A process is provided for forming a low k fluorine and carbon-containing silicon oxide dielectric material by reacting with an oxidizing agent one or more silanes including one or more organofluoro silanes characterized by the absence of aliphatic C—H bonds. In one embodiment, the process is carried out using a mild oxidizing agent. Also provided is a low dielectric constant fluorine and carbon-containing silicon oxide dielectric material for use in an integrated circuit structure containing silicon atoms bonded to oxygen atoms, silicon atoms bonded to carbon atoms, and carbon atoms bonded to fluorine atoms, where the dielectric material is characterized by the absence of aliphatic C—H bonds and where the dielectric material has a ratio of carbon atoms to silicon atoms of C:Si greater than about 1:3.

Abstract translation: 提供一种通过与氧化剂反应形成低k含氟和碳的氧化硅介电材料的方法，所述氧化剂包括一种或多种包含一种或多种以不存在脂族C-H键的有机氟硅烷的硅烷。 在一个实施方案中，该方法使用温和的氧化剂进行。 还提供了一种用于集成电路结构的低介电常数含氟和含碳氧化硅电介质材料，该集成电路结构包含与氧原子键合的硅原子，与碳原子键合的硅原子和与氟原子键合的碳原子，其中电介质材料 其特征在于不存在脂族CH键，并且其中介电材料具有大于约1:3的C：Si的碳原子与硅原子的比例。