公开(公告)号：US09275890B2

公开(公告)日：2016-03-01

申请号：US13834608

申请日：2013-03-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Jeong Soo Kim ,  Francis M. Tambwe

IPC: H01L21/76 ,  H01L21/762 ,  H01L23/544 ,  H01L21/308 ,  H01L27/088

CPC classification number: H01L23/544 ,  H01L21/3086 ,  H01L21/76224 ,  H01L21/823431 ,  H01L27/0207 ,  H01L27/0886 ,  H01L2223/54406 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2223/54453 ,  H01L2924/0002 ,  H01L2924/00

Abstract: One illustrative method disclosed herein includes forming a plurality of spaced-apart fin structures in a semiconductor substrate, wherein the fin structures define a portion of an alignment/overlay mark trench where at least a portion of an alignment/overlay mark will be formed, forming at least one layer of insulating material that overfills the alignment/overlay mark trench and removing excess portions of the layer of insulating material positioned above an upper surface of the plurality of fins to thereby define at least a portion of the alignment/overlay mark positioned within the alignment/overlay mark trench. A device disclosed herein includes a plurality of spaced-apart fin structures formed in a semiconductor substrate so as to partially define an alignment/overlay mark trench, an alignment/overlay mark consisting only of at least one insulating material positioned within the alignment/overlay mark trench, and a plurality of FinFET semiconductor devices formed in and above the substrate.

Abstract translation: 本文公开的一种说明性方法包括在半导体衬底中形成多个间隔开的翅片结构，其中鳍结构限定对准/覆盖标记沟槽的一部分，其中将形成至少一部分对准/覆盖标记，形成 至少一层绝缘材料，其过度填充对准/覆盖标记沟槽，并且移除位于多个翅片的上表面上方的绝缘材料层的多余部分，从而限定定位/重叠标记的至少一部分 对准/重叠标记沟槽。 本文公开的装置包括形成在半导体衬底中的多个间隔开的翅片结构，以便部分地限定对准/覆盖标记沟槽，对准/覆盖标记仅由位于对准/覆盖标记内的至少一个绝缘材料组成 沟槽，以及形成在衬底中和上方的多个FinFET半导体器件。

公开(公告)号：US20150372115A1

公开(公告)日：2015-12-24

申请号：US14308138

申请日：2014-06-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Shao-Ming Koh ,  Guillaume Bouche ,  Jing Wan ,  Andy C. Wei

IPC: H01L29/66 ,  H01L21/265

CPC classification number: H01L29/6653 ,  H01L21/2236 ,  H01L21/26586 ,  H01L29/0673 ,  H01L29/42376 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/775 ,  H01L29/78696

Abstract: A method of forming a nanowire device includes patterning a plurality of semiconductor material layers such that each layer has first and second exposed end surfaces. The method further includes forming doped extension regions in the first and second exposed end surfaces of the semiconductor material layers. The method further includes, after forming the doped extension regions, forming epi semiconductor material in source and drain regions of the device.

Abstract translation: 形成纳米线器件的方法包括图案化多个半导体材料层，使得每个层具有第一和第二暴露的端表面。 该方法还包括在半导体材料层的第一和第二暴露的端表面中形成掺杂的延伸区域。 该方法还包括：在形成掺杂的延伸区域之后，在器件的源极和漏极区域中形成外延半导体材料。

公开(公告)号：US20150333162A1

公开(公告)日：2015-11-19

申请号：US14279495

申请日：2014-05-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Guillaume Bouche ,  Jing Wan ,  Andy C. Wei ,  Shao-Ming Koh

IPC: H01L29/775 ,  H01L21/768 ,  H01L29/66

CPC classification number: H01L29/775 ,  B82Y10/00 ,  H01L21/28512 ,  H01L21/76879 ,  H01L21/76897 ,  H01L29/0673 ,  H01L29/1033 ,  H01L29/401 ,  H01L29/41725 ,  H01L29/42392 ,  H01L29/517 ,  H01L29/66439 ,  H01L29/78696

Abstract: A device includes a gate structure and a nanowire channel structure positioned under the gate structure. The nanowire channel structure includes first and second end surfaces. The device further includes a first insulating liner positioned on the first end surface and a second insulating liner positioned on the second end surface. The device further includes a metal-containing source contact positioned on the first insulating liner and a metal-containing drain contact positioned on the second insulating liner.

Abstract translation: 一种器件包括位于栅极结构下方的栅极结构和纳米线沟道结构。 纳米线通道结构包括第一和第二端面。 该装置还包括位于第一端表面上的第一绝缘衬垫和位于第二端表面上的第二绝缘衬垫。 该装置还包括定位在第一绝缘衬垫上的含金属源触点和位于第二绝缘衬垫上的含金属的漏极触点。

公开(公告)号：US20150279971A1

公开(公告)日：2015-10-01

申请号：US14242130

申请日：2014-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Andy C. Wei

IPC: H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66795 ,  H01L29/66818

Abstract: One method includes forming a plurality of first trenches in a semiconductor substrate to thereby define a plurality of initial fins in the substrate, removing at least one, but less than all, of the plurality of initial fins, forming a fin protection layer on at least the sidewalls of the remaining initial fins, with the fin protection layer in position, performing an etching process to extend a depth of the first trenches to thereby define a plurality of final trenches with a final trench depth, wherein the final trenches define a plurality of final fin structures that each comprise an initial fin, removing the fin protection layer, and forming a recessed layer of insulating material in the final trenches, wherein the recessed layer of insulating material has a recessed surface that exposes a portion of the final fin structures.

Abstract translation: 一种方法包括在半导体衬底中形成多个第一沟槽，从而在衬底中限定多个初始鳍片，去除多个初始鳍片中的至少一个但少于全部的初始鳍片，至少形成鳍片保护层 剩余的初始鳍片的侧壁与翅片保护层在适当的位置，执行蚀刻工艺以延伸第一沟槽的深度，从而限定具有最终沟槽深度的多个最终沟槽，其中最终沟槽限定多个 最终的翅片结构各自包括初始翅片，去除翅片保护层，以及在最终的沟槽中形成绝缘材料的凹陷层，其中绝缘材料的凹陷层具有暴露最终翅片结构的一部分的凹陷表面。

公开(公告)号：US08936986B2

公开(公告)日：2015-01-20

申请号：US13797117

申请日：2013-03-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Dae Geun Yang

IPC: H01L21/336 ,  H01L29/40

CPC classification number: H01L29/401 ,  H01L21/823431 ,  H01L21/823821 ,  H01L21/845 ,  H01L29/66545

Abstract: In one example, the method disclosed herein includes forming a shared sacrificial gate structure above at least one first fin for a first type of FinFET device and at least one second fin for a second type of FinFET device, wherein the second type is opposite to the first type, and forming a first sidewall spacer around an entire perimeter of the sacrificial gate structure in a single process operation.

Abstract translation: 在一个示例中，本文公开的方法包括在用于第一类型的FinFET器件的至少一个第一鳍上方形成共用牺牲栅极结构，以及在第二类型的FinFET器件中形成至少一个第二鳍，其中第二类型与 并且在单个工艺操作中在牺牲栅极结构的整个周边周围形成第一侧壁间隔物。

公开(公告)号：US09899268B2

公开(公告)日：2018-02-20

申请号：US14644269

申请日：2015-03-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Guillaume Bouche

IPC: H01L21/8238 ,  H01L29/10 ,  H01L27/092 ,  H01L29/78

CPC classification number: H01L21/823807 ,  H01L21/823821 ,  H01L21/823864 ,  H01L27/0924 ,  H01L29/1054 ,  H01L29/7851

Abstract: A method includes forming at least one fin in a semiconductor substrate. A fin spacer is formed on at least a first portion of the at least one fin. The fin spacer has an upper surface. The at least one fin is recessed to thereby define a recessed fin with a recessed upper surface that it is at a level below the upper surface of the fin spacer. A first epitaxial material is formed on the recessed fin. A lateral extension of the first epitaxial material is constrained by the fin spacer. A cap layer is formed on the first epitaxial material. The fin spacer is removed. The cap layer protects the first epitaxial material during the removal of the fin spacer.

公开(公告)号：US09293462B2

公开(公告)日：2016-03-22

申请号：US14167778

申请日：2014-01-29

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Shao Ming Koh ,  Guillaume Bouche ,  Jeremy A. Wahl ,  Andy C. Wei

IPC: H01L21/4763 ,  H01L27/092 ,  H01L21/311 ,  H01L29/45 ,  H01L21/8238 ,  H01L29/16 ,  H01L29/167 ,  H01L29/161

CPC classification number: H01L29/7839 ,  H01L21/02532 ,  H01L21/31111 ,  H01L21/823814 ,  H01L21/823821 ,  H01L21/823871 ,  H01L21/845 ,  H01L27/0922 ,  H01L27/0924 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/16 ,  H01L29/161 ,  H01L29/167 ,  H01L29/24 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/456 ,  H01L29/665 ,  H01L29/7848

Abstract: Integrated circuits having silicide contacts with reduced contact resistance and methods for fabricating integrated circuits having silicide contacts with reduced contact resistance are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate having selected source/drain regions and non-selected source/drain regions. The method forms a contact resistance modulation material over the selected source/drain regions. Further, the method forms a metal layer over the selected and non-selected source/drain regions. The method includes annealing the metal layer to form silicide contacts on the selected and non-selected source/drain regions.

Abstract translation: 提供了具有降低的接触电阻的硅化物接触的集成电路和用于制造具有降低的接触电阻的具有硅化物接触的集成电路的方法。 在一个实施例中，一种用于制造集成电路的方法包括提供具有所选择的源极/漏极区域和未选择的源极/漏极区域的半导体衬底。 该方法在选定的源极/漏极区域上形成接触电阻调制材料。 此外，该方法在所选择的和非选择的源/漏区上形成金属层。 该方法包括退火金属层以在所选择的和非选择的源/漏区上形成硅化物接触。

公开(公告)号：US09236258B2

公开(公告)日：2016-01-12

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/338 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US20150311081A1

公开(公告)日：2015-10-29

申请号：US14259694

申请日：2014-04-23

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ruilong Xie ,  Xiuyu Cai ,  Andy C. Wei ,  Qi Zhang ,  Ajey Poovannummoottil Jacob ,  Michael Hargrove

IPC: H01L21/28 ,  H01L29/51

CPC classification number: H01L29/513 ,  H01L21/28008 ,  H01L21/28088 ,  H01L21/28194 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/517 ,  H01L29/66545 ,  H01L29/7831 ,  H01L29/785

Abstract: One method disclosed herein includes forming a sacrificial gate structure comprised of upper and lower sacrificial gate electrodes, performing at least one etching process to define a patterned upper sacrificial gate electrode comprised of a plurality of trenches that expose a portion of a surface of the lower sacrificial gate electrode and performing another etching process through the patterned upper sacrificial gate electrode to remove the lower sacrificial gate electrode and a sacrificial gate insulation layer and thereby define a first portion of a replacement gate cavity that is at least partially positioned under the patterned upper sacrificial gate electrode.

Abstract translation: 本文公开的一种方法包括形成包括上牺牲栅极和下牺牲栅电极的牺牲栅极结构，执行至少一个蚀刻工艺以限定由多个沟槽组成的图案化的上牺牲栅电极，该多个沟槽暴露下牺牲栅表面的一部分表面 并且通过图案化的上牺牲栅电极执行另一蚀刻工艺，以去除下牺牲栅电极和牺牲栅绝缘层，从而限定至少部分地定位在图案化的上牺牲栅下方的替代栅腔的第一部分 电极。

公开(公告)号：US09105507B2

公开(公告)日：2015-08-11

申请号：US14595924

申请日：2015-01-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Andy C. Wei ,  Akshey Sehgal ,  Seung Y. Kim ,  Teck Jung Tang ,  Francis M. Tambwe

IPC: H01L29/76 ,  H01L29/10 ,  H01L27/088

CPC classification number: H01L29/1083 ,  H01L27/0886 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/785 ,  Y10S257/903

Abstract: A FinFET device includes a plurality of fin structures positioned in and above a semiconducting substrate, wherein each of the fin structures includes a first portion of the semiconducting substrate, an undoped layer of semiconducting material positioned above the first portion of the semiconducting substrate, and a dopant-containing layer of semiconducting material positioned between the first portion of the semiconducting substrate and the undoped semiconducting material, wherein the dopant material is adapted to retard diffusion of one of boron and phosphorous. A gate electrode is positioned around at least the undoped layer of semiconducting material of each of the plurality of fin structures, wherein a height level of a bottom surface of the gate electrode is positioned approximately level with or lower than a height level of a bottom of the undoped layer of semiconducting material of each of the plurality of fin structures.

Abstract translation: FinFET器件包括位于半导体衬底中和上方的多个翅片结构，其中每个翅片结构包括半导体衬底的第一部分，位于半导体衬底的第一部分上方的未掺杂的半导体材料层，以及 位于半导体衬底的第一部分和未掺杂的半导体材料之间的半导体材料含掺杂剂层，其中掺杂剂材料适于延迟硼和磷中的一种的扩散。 栅电极至少围绕多个翅片结构中的每一个的半导体材料的未掺杂层定位，其中栅电极的底表面的高度水平位于与底部的高度水平近似等于或低于 所述多个翅片结构中的每一个的未掺杂的半导体材料层。