公开(公告)号：US09478651B2

公开(公告)日：2016-10-25

申请号：US14732680

申请日：2015-06-06

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L29/06 ,  H01L29/778 ,  H01L27/088 ,  H01L21/8252 ,  H01L27/06 ,  H01L27/095 ,  H01L29/872 ,  H01L29/205 ,  H01L29/66 ,  H01L21/683 ,  G06F17/50 ,  H01L29/20 ,  H01L29/40

CPC classification number: H01L29/7786 ,  G06F17/5045 ,  G06F17/5063 ,  H01L21/6835 ,  H01L21/8252 ,  H01L27/0605 ,  H01L27/088 ,  H01L27/095 ,  H01L29/0634 ,  H01L29/2003 ,  H01L29/205 ,  H01L29/402 ,  H01L29/66462 ,  H01L29/872 ,  H01L2221/68363

Abstract: A circuit includes a first field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal; and a second field effect transistor having a gate, a first drain-source terminal, and a second drain-source terminal. The second field effect transistor and the first field effect transistor are of the same type, i.e., both re-channel transistors or both p-channel transistors. The second drain-source terminal of the first field effect transistor is coupled to the first drain-source terminal of the second field effect transistor; and the gate of the second field effect transistor is coupled to the first drain-source terminal of the second field effect transistor. The resulting three-terminal device can be substituted for a single field effect transistor that would otherwise suffer breakdown under proposed operating conditions.

Abstract translation: 电路包括具有栅极的第一场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子; 以及具有栅极的第二场效应晶体管，第一漏极 - 源极端子和第二漏极 - 源极端子。 第二场效应晶体管和第一场效应晶体管是相同类型的，即重新沟道晶体管或两个p沟道晶体管。 第一场效应晶体管的第二漏极 - 源极端子耦合到第二场效应晶体管的第一漏极 - 源极端子; 并且第二场效应晶体管的栅极耦合到第二场效应晶体管的第一漏极 - 源极端子。 所得到的三端子器件可以替代否则在所提出的工作条件下会损坏的单个场效应晶体管。

公开(公告)号：US09337436B2

公开(公告)日：2016-05-10

申请号：US14736942

申请日：2015-06-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Keith E. Fogel ,  Jeehwan Kim ,  Devendra K. Sadana ,  Tze-bin Song

IPC: H01L51/48 ,  H01L51/44 ,  H01L51/00 ,  H01L51/42

CPC classification number: H01L51/442 ,  H01L51/0013 ,  H01L51/0021 ,  H01L51/0024 ,  H01L51/0037 ,  H01L51/42 ,  H01L51/445 ,  Y02E10/549 ,  Y02P70/521

Abstract: A method for fabricating a photovoltaic device includes forming an adhesion layer on a substrate, forming a material layer on the adhesion layer and applying release tape to the material layer. The substrate is removed at a weakest interface between the adhesion layer and the substrate by mechanically pulling the release tape to form a transfer substrate including the adhesion layer, the material layer and the release tape. The transfer substrate is transferred to a target substrate to contact the adhesion layer to the target substrate. The transfer substrate includes a material sensitive to formation processes of the transfer substrate such that exposure to the formation processes of the transfer substrate is avoided by the target substrate.

公开(公告)号：US09337281B2

公开(公告)日：2016-05-10

申请号：US14803910

申请日：2015-07-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Cheng-Wei Cheng ,  Jack O. Chu ,  Devendra K. Sadana ,  Kuen-Ting Shiu ,  Yanning Sun

IPC: H01L21/336 ,  H01L29/267 ,  H01L29/772 ,  H01L29/45 ,  H01L21/02 ,  H01L21/285 ,  H01L21/322 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/267 ,  H01L21/02387 ,  H01L21/02439 ,  H01L21/02532 ,  H01L21/02538 ,  H01L21/0262 ,  H01L21/02661 ,  H01L21/02664 ,  H01L21/28575 ,  H01L21/3228 ,  H01L29/452 ,  H01L29/66522 ,  H01L29/772 ,  H01L29/78

Abstract: A semiconductor structure includes a III-V monocrystalline layer and a germanium surface layer. An interlayer is formed directly between the III-V monocrystalline layer and the germanium surface layer from a material selected to provide stronger nucleation bonding between the interlayer and the germanium surface layer than nucleation bonding that would be achievable directly between the III-V monocrystalline layer and the germanium surface layer such that a continuous, relatively defect-free germanium surface layer is provided.

公开(公告)号：US09331229B2

公开(公告)日：2016-05-03

申请号：US14147939

申请日：2014-01-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Stephen W. Bedell ,  Bahman Hekmatshoartabari ,  Devendra K. Sadana ,  Ghavam G. Shahidi ,  Davood Shahrjerdi

IPC: H01L31/00 ,  H01L21/00 ,  H01L31/075 ,  H01L31/0304 ,  H01L31/074

CPC classification number: H01L31/075 ,  H01L31/03046 ,  H01L31/074 ,  Y02E10/544 ,  Y02P70/521

Abstract: An InxGa1-xAs interlayer is provided between a III-V base and an intrinsic amorphous semiconductor layer of a heterojunction III-V solar cell structure. Improved surface passivation and open circuit voltage may be obtained through the incorporation of the interlayer within the structure.

Abstract translation: 在III-V基极和异质结III-V族太阳能电池结构的本征非晶半导体层之间提供In x Ga 1-x As夹层。 可以通过在结构内并入中间层来获得改进的表面钝化和开路电压。

公开(公告)号：US09459797B2

公开(公告)日：2016-10-04

申请号：US14153728

申请日：2014-01-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Christos Dimitrakopoulos ,  Augustin J. Hong ,  Jeehwan Kim ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L31/02 ,  G06F3/06 ,  H04W8/06 ,  H01L31/0236 ,  G06F11/07 ,  G06F12/02 ,  H04L29/08 ,  G06F11/10 ,  H04W8/04

CPC classification number: G06F3/061 ,  G06F3/064 ,  G06F3/0647 ,  G06F3/0653 ,  G06F3/0689 ,  G06F11/0727 ,  G06F11/1076 ,  G06F12/02 ,  H01L31/02366 ,  H04L67/1002 ,  H04W8/04 ,  H04W8/065 ,  Y02E10/50

Abstract: A method for fabricating a photovoltaic device includes applying a diblock copolymer layer on a substrate and removing a first polymer material from the diblock copolymer layer to form a plurality of distributed pores. A pattern forming layer is deposited on a remaining surface of the diblock copolymer layer and in the pores in contact with the substrate. The diblock copolymer layer is lifted off and portions of the pattern forming layer are left in contact with the substrate. The substrate is etched using the pattern forming layer to protect portions of the substrate to form pillars in the substrate such that the pillars provide a radiation absorbing structure in the photovoltaic device.

Abstract translation: 一种制造光伏器件的方法包括在基片上涂布二嵌段共聚物层，并从二嵌段共聚物层除去第一聚合物材料以形成多个分布孔。 图案形成层沉积在二嵌段共聚物层的剩余表面上和与基材接触的孔中。 剥离二嵌段共聚物层，使图案形成层的一部分与基板保持接触。 使用图案形成层蚀刻衬底以保护衬底的部分以在衬底中形成柱，使得柱在光伏器件中提供辐射吸收结构。

公开(公告)号：US09647063B2

公开(公告)日：2017-05-09

申请号：US14797945

申请日：2015-07-13

Applicant: GLOBALFOUNDRIES INC. ,  King Abdulaziz City for Science and Technology

Inventor： Maha M. Khayyat ,  Devendra K. Sadana ,  Brent A. Wacaser

IPC: H01L29/20 ,  H01L29/06 ,  H01L21/20 ,  H01L21/30 ,  H01L29/66 ,  H01L29/02

CPC classification number: H01L29/0676 ,  H01L21/20 ,  H01L21/30 ,  H01L29/02 ,  H01L29/20 ,  H01L29/66

Abstract: A method of fabricating templated semiconductor nanowires on a surface of a semiconductor substrate for use in semiconductor device applications is provided. The method includes controlling the spatial placement of the semiconductor nanowires by using an oxygen reactive seed material. The present invention also provides semiconductor structures including semiconductor nanowires. In yet another embodiment, patterning of a compound semiconductor substrate or other like substrate which is capable of forming a compound semiconductor alloy with an oxygen reactive element during a subsequent annealing step is provided. This embodiment provides a patterned substrate that can be used in various applications including, for example, in semiconductor device manufacturing, optoelectronic device manufacturing and solar cell device manufacturing.

公开(公告)号：US09236251B2

公开(公告)日：2016-01-12

申请号：US14705425

申请日：2015-05-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Can Bayram ,  Cheng-Wei Cheng ,  Tak H. Ning ,  Devendra K. Sadana ,  Kuen-Ting Shiu

IPC: H01L21/02 ,  H01L29/267 ,  H01L29/06

CPC classification number: H01L21/0254 ,  H01L21/02365 ,  H01L21/02381 ,  H01L21/02433 ,  H01L21/0245 ,  H01L21/02516 ,  H01L21/0262 ,  H01L21/02658 ,  H01L21/02664 ,  H01L21/2007 ,  H01L29/0649 ,  H01L29/2003 ,  H01L29/267

Abstract: Various methods to integrate a Group III nitride material on a silicon material are provided. In one embodiment, the method includes providing a structure including a (100) silicon layer, a (111) silicon layer located on an uppermost surface of the (100) silicon layer, a Group III nitride material layer located on an uppermost surface of the (111) silicon layer, and a blanket layer of dielectric material located on an uppermost surface of the Group III nitride material layer. Next, an opening is formed through the blanket layer of dielectric material, the Group III nitride material layer, the (111) Si layer and within a portion of the (100) silicon layer. A dielectric spacer is then formed within the opening. An epitaxial semiconductor material is then formed on an exposed surface of the (100) silicon layer within the opening and thereafter planarization is performed.