公开(公告)号：US09922973B1

公开(公告)日：2018-03-20

申请号：US15611184

申请日：2017-06-01

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Thai Doan

IPC: H01L21/76 ,  H01L27/088 ,  H01L29/08 ,  H01L29/10 ,  H01L27/02 ,  H01L29/06 ,  H01L21/8234 ,  H01L21/761 ,  H01L21/764 ,  H01L21/02 ,  H01L21/763

CPC classification number: H01L27/088 ,  H01L21/761 ,  H01L21/763 ,  H01L21/764 ,  H01L21/823481 ,  H01L21/823493 ,  H01L29/0603 ,  H01L29/0646 ,  H01L29/0649 ,  H01L29/0847 ,  H01L29/1079 ,  H01L29/1095

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.

公开(公告)号：US10833153B2

公开(公告)日：2020-11-10

申请号：US15703220

申请日：2017-09-13

Applicant: GLOBALFOUNDRIES INC.

Inventor： Qizhi Liu ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Anthony K. Stamper

IPC: H01L29/06 ,  H01L27/12 ,  H01L29/10 ,  H01L21/02 ,  H01L21/84 ,  H01L21/764 ,  H01L21/762 ,  H01L29/786

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a switch with local silicon on insulator (SOI) and deep trench isolation structures and methods of manufacture. The structure a structure comprises an air gap located under a device region and bounded by an upper etch stop layer and deep trench isolation structures.

公开(公告)号：US10580893B2

公开(公告)日：2020-03-03

申请号：US15947364

申请日：2018-04-06

Applicant: GLOBALFOUNDRIES INC.

Inventor： Siva P. Adusumilli ,  Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan

IPC: H01L29/78 ,  H01L21/762 ,  H01L21/84 ,  H01L21/324 ,  H01L23/10 ,  H01L29/06 ,  H01L29/10 ,  H01L27/12 ,  H01L21/02 ,  H01L21/8238

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to sealed cavity structures having a non-planar surface features and methods of manufacture. The structure includes a cavity formed in a substrate material. The cavity is covered with epitaxial material that has a non-planar surface topography which imparts a stress component on a transistor.

公开(公告)号：US10511143B2

公开(公告)日：2019-12-17

申请号：US15692136

申请日：2017-08-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： John J. Ellis-Monaghan ,  Sebastian Ventrone ,  Vibhor Jain ,  Yves Ngu

IPC: H01S5/00 ,  H01S5/062 ,  H01S5/022 ,  H01S5/026 ,  H01S5/183 ,  H01S5/223 ,  H01S5/22

Abstract: Structures for integrated lasers, systems including integrated lasers, and associated fabrication methods. A ring waveguide and a seed region are arranged interior of the ring waveguide. A laser strip extends across a portion of the ring waveguide. The laser strip has an end contacting the seed region and another opposing end. The laser strip includes a laser medium and a p-n junction capable of generating electromagnetic radiation. The p-n junction of the laser strip is aligned with a portion of the ring waveguide.

公开(公告)号：US10509244B1

公开(公告)日：2019-12-17

申请号：US16216027

申请日：2018-12-11

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Steven M. Shank ,  Anthony K. Stamper ,  John J. Ellis-Monaghan ,  Vibhor Jain ,  John J. Pekarik

IPC: G02F1/01

Abstract: Structures for an optical switch, structures for an optical router, and methods of fabricating a structure for an optical switch. A phase change layer is arranged proximate to a waveguide core, and a heater is formed proximate to the phase change layer. The phase change layer is composed of a phase change material having a first state with a first refractive index at a first temperature and a second state with a second refractive index at a second temperature. The heater is configured to selectively transfer heat to the phase change layer for transitioning between the first state and the second state.

公开(公告)号：US10461152B2

公开(公告)日：2019-10-29

申请号：US15645655

申请日：2017-07-10

Applicant: GLOBALFOUNDRIES INC.

Inventor： Anthony K. Stamper ,  Steven M. Shank ,  John J. Ellis-Monaghan ,  Siva P. Adusumilli

IPC: H01L21/764 ,  H01L29/06 ,  H01L23/66 ,  H01L29/10 ,  H01L29/78

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to radio frequency (RF) switches with airgap structures and methods of manufacture. The structure includes a substrate with at least one airgap structure formed in a well region under at least one gate structure, and which extends to a junction formed by a source/drain region of the at least one gate structure.

公开(公告)号：US10090330B2

公开(公告)日：2018-10-02

申请号：US15901997

申请日：2018-02-22

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  Terence B. Hook ,  Kirk D. Peterson

IPC: H01L27/12 ,  H01L29/10 ,  H01L21/66 ,  H01L21/84 ,  H01L27/11 ,  H01L21/762 ,  H01L29/66 ,  H01L29/06

Abstract: A method for fabricating a fully depleted silicon on insulator (FDSOI) device is described. A charge trapping layer in a buried oxide layer is provided on a semiconductor substrate. A backgate well in the semiconductor substrate is provided under the charge trapping layer. A device structure including a gate structure, source and drain regions is disposed over the buried oxide layer. A charge is trapped in the charge trapping layer. The threshold voltage of the device is partially established by the charge trapped in the charge trapping layer. Different aspects of the invention include the structure of the FDSOI device and a method of tuning the charge trapped in the charge trapping layer of the FDSOI device.

公开(公告)号：US09647165B2

公开(公告)日：2017-05-09

申请号：US14830870

申请日：2015-08-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven M. Shank ,  John J. Ellis-Monaghan ,  Marwan H. Khater ,  Jason S. Orcutt

IPC: H01L31/105 ,  H01L31/0232 ,  H01L31/109 ,  H01L31/028 ,  H01L31/0352 ,  H01L31/18

CPC classification number: H01L31/1812 ,  H01L31/022408 ,  H01L31/028 ,  H01L31/0312 ,  H01L31/035272 ,  H01L31/03529 ,  H01L31/03921 ,  H01L31/1037 ,  H01L31/109 ,  H01L31/1864 ,  H01L31/1872 ,  Y02E10/50

Abstract: Various particular embodiments include a method for forming a photodetector, including: forming a structure including a barrier layer disposed between a layer of doped silicon (Si) and a layer of germanium (Ge), the barrier layer including a crystallization window; and annealing the structure to convert, via the crystallization window, the Ge to a first composition of silicon germanium (SiGe) and the doped Si to a second composition of SiGe.

公开(公告)号：US09466753B1

公开(公告)日：2016-10-11

申请号：US14837812

申请日：2015-08-27

Applicant: GLOBALFOUNDRIES INC.

Inventor： John J. Ellis-Monaghan ,  John C. S. Hall ,  Marwan H. Khater ,  Edward W. Kiewra ,  Steven M. Shank

IPC: H01L31/18 ,  H01L31/103 ,  H01L31/0203 ,  H01L31/028 ,  H01L27/144

CPC classification number: H01L31/1808 ,  H01L27/1443 ,  H01L27/1446 ,  H01L27/14629 ,  H01L31/0203 ,  H01L31/02161 ,  H01L31/02327 ,  H01L31/028 ,  H01L31/103 ,  H01L31/105 ,  H01L31/1872

Abstract: Disclosed are a method of forming a photodetector and a photodetector structure. In the method, a polycrystalline or amorphous light-absorbing layer is formed on a dielectric layer such that it is in contact with a monocrystalline semiconductor core of an optical waveguide. The light-absorbing layer is then encapsulated in one or more strain-relief layers and a rapid melting growth (RMG) process is performed to crystallize the light-absorbing layer. The strain-relief layer(s) are tuned for controlled strain relief so that, during the RMG process, the light-absorbing layer remains crack-free. The strain-relief layer(s) are then removed and an encapsulation layer is formed over the light-absorbing layer (e.g., filling in surface pits that developed during the RMG process). Subsequently, dopants are implanted through the encapsulation layer to form diffusion regions for PIN diode(s). Since the encapsulation layer is relatively thin, desired dopant profiles can be achieved within the diffusion regions.

Abstract translation: 公开了一种形成光电检测器和光电检测器结构的方法。 在该方法中，在电介质层上形成多晶或非晶光吸收层，使其与光波导的单晶半导体芯接触。 然后将光吸收层封装在一个或多个应变消除层中，并进行快速熔融生长（RMG）工艺以使光吸收层结晶。 调节应变消除层以控制应变消除，使得在RMG过程期间，光吸收层保持无裂纹。 然后去除应变消除层，并且在光吸收层上形成封装层（例如，填充在RMG工艺期间产生的表面凹坑中）。 随后，通过封装层注入掺杂剂以形成用于PIN二极管的扩散区域。 由于封装层相对较薄，所以可以在扩散区域内实现所需的掺杂分布。

公开(公告)号：US09397203B2

公开(公告)日：2016-07-19

申请号：US14677460

申请日：2015-04-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： John Z. Colt, Jr. ,  John J. Ellis-Monaghan ,  Leah M. Pastel ,  Steven M. Shank

IPC: H01L29/66 ,  H01L29/737 ,  H01L29/735 ,  H01L29/06 ,  H01L29/10 ,  H01L29/08 ,  H01L29/73

CPC classification number: H01L29/737 ,  H01L29/0649 ,  H01L29/0821 ,  H01L29/1008 ,  H01L29/66242 ,  H01L29/6625 ,  H01L29/66265 ,  H01L29/7317 ,  H01L29/735

Abstract: Device structures, fabrication methods, and design structures for a bipolar junction transistor. A first terminal of the bipolar junction transistor is formed from a section of a device layer of a semiconductor-on-insulator wafer. An intrinsic base of the bipolar junction transistor is formed from an epitaxially-grown section of a first semiconductor layer, which is coextensive with a sidewall of the section of the device layer. A second terminal of the bipolar junction transistor is formed from a second semiconductor layer that is coextensive with the epitaxially-grown section of the first semiconductor layer. The epitaxially-grown section of a first semiconductor layer defines a first junction with the section of the device layer, and the second semiconductor layer defines a second junction with the epitaxially-grown section of the first semiconductor layer.