公开(公告)号：US20180061842A1

公开(公告)日：2018-03-01

申请号：US15248889

申请日：2016-08-26

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L29/66 ,  H01L21/311 ,  H01L21/768 ,  H01L29/78 ,  H01L23/535

CPC classification number: H01L27/1104 ,  H01L21/31111 ,  H01L21/31144 ,  H01L21/76895 ,  H01L23/535 ,  H01L27/11 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/785

Abstract: Semiconductor devices and methods of fabricating the semiconductor devices for forming conductive paths between fins for contact-to-gate shorting. One method includes, for instance: obtaining wafer with a substrate, at least one fin, at least one hard mask, and an oxide layer; etching the oxide layer to reveal at least one of a portion of the hard masks; forming sacrificial pillars over the substrate; forming sacrificial gates, wherein at least one sacrificial gate contacts at least one sacrificial pillar; growing an epitaxial layer between the at least one sacrificial gate and the at least one sacrificial pillar; starting a RMG process on the sacrificial gates; etching to remove the sacrificial pillars and form pillar openings; and completing the RMG process to fill the pillar openings and the gate openings with a metal.

公开(公告)号：US20180047734A1

公开(公告)日：2018-02-15

申请号：US15792527

申请日：2017-10-24

Applicant: GLOBALFOUNDRIES INC.

Inventor： Hui ZANG ,  Min-hwa CHI

IPC: H01L27/11 ,  H01L27/092 ,  H01L21/8238

CPC classification number: H01L27/1104 ,  H01L21/823807 ,  H01L21/823821 ,  H01L21/823828 ,  H01L27/092 ,  H01L27/0924

Abstract: A semiconductor structure includes a semiconductor substrate, at least one first elongated region of n-type or p-type, and at least one other second elongated region of the other of n-type or p-type, the first and second elongated regions crossing such that the first elongated region and the second elongated region intersect at a common area, and a shared gate structure over each common area.

公开(公告)号：US20170278949A1

公开(公告)日：2017-09-28

申请号：US15620082

申请日：2017-06-12

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen-Pin PENG ,  Min-hwa CHI

IPC: H01L29/66 ,  H01L21/225 ,  H01L21/324

CPC classification number: H01L29/66636 ,  H01L21/2253 ,  H01L21/26506 ,  H01L29/6659 ,  H01L29/7847 ,  H01L29/7848

Abstract: Disclosed are methods for stress memorization techniques. In one illustrative embodiment, the present disclosure is directed to a method involving fabricating an NMOS transistor device having a substrate and a gate structure disposed over the substrate, the substrate including a channel region underlying, at least partially, the gate structure, the fabricating including: forming a source and drain cavity in the substrate; with an in situ doped semiconductor material, epitaxially growing a source and drain region within the source and drain cavity; performing an amorphization ion implantation process by implanting an amorphization ion material into the source and drain region; forming a capping material layer above the NMOS transistor device; with the capping material layer in position, performing a stress forming anneal process to thereby form stacking faults in the source and drain region; and removing the capping material layer.

公开(公告)号：US20170207118A1

公开(公告)日：2017-07-20

申请号：US14995838

申请日：2016-01-14

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wen Pin PENG ,  Min-hwa CHI ,  Yue HU

IPC: H01L21/768 ,  H01L29/08 ,  H01L23/535 ,  H01L29/06 ,  H01L29/66 ,  H01L21/28

CPC classification number: H01L21/76829 ,  H01L21/28123 ,  H01L21/76897 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66636 ,  H01L29/78

Abstract: A starting semiconductor structure for a RMG process includes a semiconductor substrate, transistors in process having dummy gates and electrically isolated by isolation regions. The dummy gates are replaced with metal gates and gate caps, the structure being planarized after replacing the gate. A cap layer is formed over the planarized structure, and trenches are formed through the cap to expose source and drain regions of the transistors, which allows for self-aligned source and drain contacts. Semiconductor structures including the source and drain trenches for self-aligned source/drain contacts are also presented.

公开(公告)号：US20170092583A1

公开(公告)日：2017-03-30

申请号：US14867341

申请日：2015-09-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Ajey P. JACOB ,  Suraj K. PATIL ,  Min-hwa CHI

IPC: H01L23/525 ,  H01L23/522

CPC classification number: H01L23/5256 ,  H01L23/5226

Abstract: Programmable via devices and fabrication methods thereof are presented. The programmable via devices include, for instance, a first metal layer and a second metal layer electrically connected by a via link. The via link includes a semiconductor portion and a metal portion, where the via link facilitates programming of the programmable via device by applying a programming current through the via link to migrate materials between the semiconductor portion and the metal portion to facilitate a change of an electrical resistance of the via link. In one embodiment, the programming current facilitates formation of at least one gap region within the via link, the at least one gap region facilitating the change of the electrical resistance of the via link.

公开(公告)号：US20170084718A1

公开(公告)日：2017-03-23

申请号：US15367366

申请日：2016-12-02

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xusheng WU ,  Min-hwa CHI ,  Edmund Kenneth BANGHART

IPC: H01L29/66 ,  H01L29/16 ,  H01L29/10 ,  H01L29/78 ,  H01L29/06

CPC classification number: H01L29/66537 ,  H01L29/0653 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/16 ,  H01L29/6656 ,  H01L29/66795 ,  H01L29/66803 ,  H01L29/66818 ,  H01L29/7851 ,  H01L29/7853

Abstract: A method of forming a FinFET fin with low-doped and a highly-doped active portions and/or a FinFET fin having tapered sidewalls for Vt tuning and multi-Vt schemes and the resulting device are provided. Embodiments include forming an Si fin, the Si fin having a top active portion and a bottom active portion; forming a hard mask on a top surface of the Si fin; forming an oxide layer on opposite sides of the Si fin; implanting a dopant into the Si fin; recessing the oxide layer to reveal the active top portion of the Si fin; etching the top active portion of the Si fin to form vertical sidewalls; forming a nitride spacer covering each vertical sidewall; recessing the recessed oxide layer to reveal the active bottom portion of the Si fin; and tapering the active bottom portion of the Si fin.

公开(公告)号：US20160190324A1

公开(公告)日：2016-06-30

申请号：US15059793

申请日：2016-03-03

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wei Hua TONG ,  Tien-Ying LUO ,  Yan Ping SHEN ,  Feng ZHOU ,  Jun LIAN ,  Haoran SHI ,  Min-hwa CHI ,  Jin Ping LIU ,  Haiting WANG ,  Seung KIM

IPC: H01L29/78 ,  H01L29/51 ,  H01L29/66 ,  H01L21/02 ,  H01L21/28

CPC classification number: H01L29/7851 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02312 ,  H01L21/02332 ,  H01L21/0234 ,  H01L21/28185 ,  H01L21/28202 ,  H01L21/28211 ,  H01L21/321 ,  H01L21/324 ,  H01L29/511 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66795 ,  H01L29/785

Abstract: Fin-type transistor fabrication methods and structures are provided having one or more nitrided conformal layers, to improve reliability of the semiconductor device. The method includes, for example, providing at least one material layer disposed, in part, conformally over a fin extending above a substrate, the material layer(s) including a gate dielectric layer; and performing a conformal nitridation process over an exposed surface of the material layer(s), the conformal nitridation process forming an exposed, conformal nitrided surface.

公开(公告)号：US20160111322A1

公开(公告)日：2016-04-21

申请号：US14974772

申请日：2015-12-18

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L21/762 ,  H01L21/225 ,  H01L29/66 ,  H01L21/283

CPC classification number: H01L21/76243 ,  H01L21/2253 ,  H01L21/283 ,  H01L29/66795 ,  H01L29/7849 ,  H01L29/785

Abstract: There is set forth herein in one embodiment a FinFET semiconductor device having a fin extending from a bulk silicon substrate, wherein there is formed wrapped around a portion of the fin a gate, and wherein proximate a channel area of the fin aligned to the gate there is formed a local buried oxide region aligned to the gate. In one embodiment, the local buried oxide region is formed below a channel area of the fin.

公开(公告)号：US20160049488A1

公开(公告)日：2016-02-18

申请号：US14458941

申请日：2014-08-13

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yan Ping SHEN ,  Haiting WANG ,  Min-hwa CHI ,  Yong Meng LEE

IPC: H01L29/423 ,  H01L21/3213 ,  H01L21/8234 ,  H01L27/105 ,  H01L27/088 ,  H01L29/66 ,  H01L27/11

CPC classification number: H01L29/42376 ,  H01L21/823828 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66628 ,  H01L29/7834

Abstract: A semiconductor structure with wide-bottom and/or wide-top gates includes a semiconductor substrate, a source region(s), a drain region(s) associated with the source region(s), and a gate(s) associated with the source region(s) and the drain region(s) having a top portion and a bottom portion. One of the top portion and the bottom portion of the gate(s) is wider than the other of the top portion and bottom portion. The wide-bottom gate is created using a dummy wide-bottom gate etched from a layer of dummy gate material, creating spacers for the dummy gate, removing the dummy gate material and filling the opening created with conductive material. For the wide-top gate, first and second spacers are included, and instead of removing all the dummy gate material, only a portion is removed, exposing the first spacers. The exposed portion of the first spacers may either be completely or partially removed (e.g., tapered), in order to increase the area of the top portion of the gate to be filled.

Abstract translation: 具有宽底部和/或宽顶部栅极的半导体结构包括半导体衬底，源极区域，与源极区域相关联的漏极区域以及与所述源极区域相关联的栅极 源极区和漏极区具有顶部和底部。 栅极的顶部和底部之一比顶部和底部中的另一个宽。 使用从虚拟栅极材料层蚀刻的虚拟宽底栅极创建宽底栅极，产生用于伪栅极的间隔物，去除虚拟栅极材料并填充由导电材料形成的开口。 对于宽顶栅，包括第一和第二间隔物，而不是去除所有的虚拟栅极材料，仅去除一部分，暴露第一间隔物。 第一间隔件的暴露部分可以被完全或部分地去除（例如，渐缩），以增加要填充的浇口顶部的面积。

公开(公告)号：US20150200298A1

公开(公告)日：2015-07-16

申请号：US14156565

申请日：2014-01-16

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yanxiang LIU ,  Min-hwa CHI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/417 ,  H03C3/02 ,  H01L29/161 ,  H01L21/265 ,  H01L21/324 ,  H01L29/66 ,  H01L29/08

CPC classification number: H03C3/145 ,  H01L27/088 ,  H01L29/0688 ,  H01L29/0847 ,  H01L29/161 ,  H01L29/66356 ,  H01L29/66568 ,  H01L29/66977 ,  H01L29/7391 ,  H01L29/78 ,  H01L29/7848 ,  H03C3/02 ,  H03C3/245 ,  H03D7/125

Abstract: Tunneling field effect transistors and fabrication methods thereof are provided, which include: obtaining a gate structure disposed over a substrate structure; and providing a source region and a drain region within the substrate structure separated by a channel region, the channel region underlying, at least partially, the gate structure, and the providing including: modifying the source region to attain a narrowed source region bandgap; and modifying the drain region to attain a narrowed drain region bandgap, the narrowed source region bandgap and the narrowed drain region bandgap facilitating quantum tunneling of charge carriers from the source region or the drain region to the channel region. Devices including digital modulation circuits with one or more tunneling field effect transistor(s) are also provided.

Abstract translation: 提供隧道场效应晶体管及其制造方法，其包括：获得设置在衬底结构上的栅极结构; 以及在由沟道区分隔开的衬底结构内提供源极区和漏极区，至少部分地位于栅极结构的下方的沟道区，并且所述提供包括：修改源极区以获得变窄的源极区带隙; 并且修改漏极区以获得窄的漏极区带隙，窄的源极区带隙和窄的漏极区带隙，有助于电荷载流子从源区或漏区到沟道区的量子隧穿。 还提供了包括具有一个或多个隧穿场效应晶体管的数字调制电路的装置。