公开(公告)号：US20150214330A1

公开(公告)日：2015-07-30

申请号：US14163687

申请日：2014-01-24

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Jing WAN ,  Jin Ping LIU ,  Guillaume BOUCHE ,  Andy WEI ,  Lakshmanan H. VANAMURTHY ,  Cuiqin XU ,  Sridhar KUCHIBHATLA ,  Rama KAMBHAMPATI ,  Xiuyu CAI

IPC: H01L29/66 ,  H01L21/311 ,  H01L21/28 ,  H01L21/3105

CPC classification number: H01L29/66545 ,  H01L21/28079 ,  H01L21/28088 ,  H01L21/31055 ,  H01L21/31111 ,  H01L29/165 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method includes providing a gate structure having a gate, a first spacer along at least one side of the gate and an interlayer dielectric on at least one of the gate and the first spacer. The interlayer dielectric is removed to reveal the first spacer. The first spacer is removed and a second spacer is deposited on at least one side of the gate. The second spacer is formed of material having a lower dielectric constant than the first spacer.

Abstract translation: 一种方法包括提供具有栅极的栅极结构，沿栅极的至少一侧的第一间隔物，以及至少一个栅极和第一间隔物上的层间电介质。 去除层间电介质以露出第一间隔物。 去除第一间隔物并且在栅极的至少一侧沉积第二间隔物。 第二间隔物由具有比第一间隔物低的介电常数的材料形成。

公开(公告)号：US20140353734A1

公开(公告)日：2014-12-04

申请号：US13909328

申请日：2013-06-04

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Ruilong XIE ,  Xiuyu CAI ,  Vimal KAMINENI ,  Kangguo CHENG ,  Ali KHAKIFIROOZ

IPC: H01L21/28 ,  H01L29/417 ,  H01L29/423 ,  H01L21/283

CPC classification number: H01L29/42376 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/283 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76885 ,  H01L21/76897 ,  H01L21/823425 ,  H01L21/823475 ,  H01L23/485 ,  H01L23/53266 ,  H01L29/41775 ,  H01L29/665 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66628 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures with reduced gate and/or contact resistances and fabrication methods are provided. The method includes: providing a semiconductor device, which includes forming a transistor of the semiconductor device, where the transistor forming includes: forming a T-shaped gate for the transistor, the T-shaped gate being T-shaped in elevational cross-section; and forming an inverted-T-shaped contact to an active region of the transistor, the inverted-T-shaped contact including a conductive structure with an inverted T-shape in elevational cross-section.

Abstract translation: 提供具有减小的栅极和/或接触电阻的半导体结构和制造方法。 该方法包括：提供半导体器件，其包括形成半导体器件的晶体管，其中晶体管形成包括：形成用于晶体管的T形栅极，T形栅极呈垂直截面为T形; 并且在晶体管的有源区域形成倒T形的接触，所述倒T形接触件包括在横截面上具有倒T形的导电结构。

公开(公告)号：US20140209563A1

公开(公告)日：2014-07-31

申请号：US13754170

申请日：2013-01-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI

IPC: H05K3/00

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

公开(公告)号：US20160181384A1

公开(公告)日：2016-06-23

申请号：US14581741

申请日：2014-12-23

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen YEH

IPC: H01L29/423 ,  H01L29/66 ,  H01L29/40 ,  H01L29/78

CPC classification number: H01L29/4236 ,  H01L29/401 ,  H01L29/42364 ,  H01L29/42384 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66772 ,  H01L29/66795 ,  H01L29/7825 ,  H01L29/78654

Abstract: The present disclosure is directed to a gate structure for a transistor. The gate structure is formed on a substrate and includes a trench. There are sidewalls that line the trench. The sidewalls have a first dimension at a lower end of the trench and a second dimension at an upper end of the trench. The first dimension being larger than the second dimension, such that the sidewalls are tapered from a lower region to an upper region. A high k dielectric liner is formed on the sidewalls and a conductive liner is formed on the high k dielectric liner. A conductive material is in the trench and is adjacent to the conductive liner. The conductive material has a first dimension at the lower end of the trench that is smaller than a second dimension at the upper end of the trench.

Abstract translation: 本公开涉及晶体管的栅极结构。 栅极结构形成在衬底上并且包括沟槽。 有沟槽划线的侧壁。 侧壁在沟槽的下端具有第一尺寸，在沟槽的上端具有第二尺寸。 第一尺寸大于第二尺寸，使得侧壁从下部区域向上部区域逐渐变细。 在侧壁上形成高k电介质衬垫，并且在高k电介质衬垫上形成导电衬垫。 导电材料在沟槽中并且与导电衬垫相邻。 导电材料在沟槽的下端具有小于沟槽上端的第二尺寸的第一尺寸。

公开(公告)号：US20160104799A1

公开(公告)日：2016-04-14

申请号：US14511715

申请日：2014-10-10

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Yi QI ,  Catherine B. LABELLE ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L29/10 ,  H01L29/06 ,  H01L29/66 ,  H01L29/423 ,  H01L21/84 ,  H01L21/762 ,  H01L27/12 ,  H01L29/775

CPC classification number: H01L29/7849 ,  B82Y10/00 ,  H01L21/76224 ,  H01L21/76229 ,  H01L21/76283 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0653 ,  H01L29/0673 ,  H01L29/1054 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66545 ,  H01L29/6656 ,  H01L29/66818 ,  H01L29/775

Abstract: A dual-strained Si and SiGe FinFET device with dielectric isolation and a dual-strained nanowire device and methods of forming them are provided. Embodiments include a SiGe SRB formed on a silicon substrate, the SRB having a first region and a second region; a first and a second dielectric isolation layer formed on the first region and on the second region of the SiGe SRB, respectively; a tensile strained Si fin formed on the first dielectric isolation layer; a compressive strained SiGe fin formed on the second dielectric isolation layer; first source/drain regions formed at opposite sides of the tensile strained Si fin; second source/drain regions formed at opposite sides of the compressive strained SiGe fin; a first RMG formed between the first source/drain regions; and a second RMG formed between the second source/drain regions.

Abstract translation: 提供具有绝缘隔离的双应变Si和SiGe FinFET器件和双应变纳米线器件及其形成方法。 实施例包括形成在硅衬底上的SiGe SRB，SRB具有第一区域和第二区域; 分别形成在SiGe SRB的第一区域和第二区域上的第一和第二介电隔离层; 形成在第一介电隔离层上的拉伸应变Si翅片; 形成在所述第二介电隔离层上的压缩应变SiGe鳍; 形成在拉伸应变Si翅片的相对侧的第一源极/漏极区域; 形成在压缩应变SiGe翅片的相对侧的第二源极/漏极区域; 形成在第一源/漏区之间的第一RMG; 以及形成在第二源/漏区之间的第二RMG。

公开(公告)号：US20150243660A1

公开(公告)日：2015-08-27

申请号：US14189509

申请日：2014-02-25

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES INC.

Inventor： Qing LIU ,  Xiuyu CAI ,  Chun-chen YEH ,  Ruilong XIE

IPC: H01L27/092 ,  H01L21/285 ,  H01L21/02 ,  H01L29/45 ,  H01L21/8238

Abstract: A method for fabricating a CMOS integrated circuit structure and the CMOS integrated circuit structure. The method includes creating one or more n-type wells, creating one or more p-type wells, creating one or more pFET source-drains embedded in each of the one or more n-type wells, creating one or more nFET source-drains embedded in each of the one or more p-type wells, creating a pFET contact overlaying each of the one or more pFET source-drains, and creating an nFET contact overlaying each of the one or more nFET source-drains. A material of each of the one or more pFET source-drains includes silicon doped with a p-type material; a material of each of the one or more nFET source-drains includes silicon doped with an n-type material; a material of each pFET contact includes nickel silicide; and a material of each nFET contact comprises titanium silicide.

Abstract translation: 一种制造CMOS集成电路结构的方法和CMOS集成电路结构。 该方法包括产生一个或多个n型阱，产生一个或多个p型阱，产生嵌入在一个或多个n型阱中的每一个中的一个或多个pFET源极漏极，产生一个或多个nFET源极漏极 嵌入在所述一个或多个p型阱中的每一个中，产生覆盖所述一个或多个pFET源极漏极中的每一个的pFET触点，以及产生覆盖所述一个或多个nFET源极漏极中的每一个的nFET触点。 一个或多个pFET源极漏极中的每一个的材料包括掺杂有p型材料的硅; 一个或多个nFET源极漏极中的每一个的材料包括掺杂有n型材料的硅; 每个pFET触点的材料包括硅化镍; 并且每个nFET接触的材料包括硅化钛。

公开(公告)号：US20150137273A1

公开(公告)日：2015-05-21

申请号：US14080842

申请日：2013-11-15

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI ,  Hoon KIM

IPC: H01L29/66 ,  H01L29/49 ,  H01L29/78

CPC classification number: H01L29/66545 ,  H01L21/28247 ,  H01L21/76834 ,  H01L21/76856 ,  H01L21/76897 ,  H01L29/4958 ,  H01L29/6653 ,  H01L29/78

Abstract: A methodology for forming a self-aligned contact (SAC) that exhibits reduced likelihood of a contact-to-gate short circuit failure and the resulting device are disclosed. Embodiments may include forming a replacement metal gate, with spacers at opposite sides thereof, on a substrate, forming a recess in an upper surface of the spacers along outer edges of the replacement metal gate, and forming an aluminum nitride (AlN) cap over the metal gate and in the recess.

Abstract translation: 公开了一种用于形成展现出接触到栅极短路故障的可能性降低的自对准接触（SAC）的方法以及所得到的器件。 实施例可以包括在衬底上形成具有相对侧面的间隔物的替换金属栅极，在替代金属栅极的外边缘上在间隔物的上表面中形成凹部，并在该金属栅极上形成氮化铝（AlN） 金属门和凹槽。

公开(公告)号：US20160190325A1

公开(公告)日：2016-06-30

申请号：US14584161

申请日：2014-12-29

Applicant: STMICROELECTRONICS, INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION ,  GLOBALFOUNDRIES Inc.

Inventor： Qing LIU ,  Nicholas LOUBET ,  Chun-chen YEH ,  Ruilong XIE ,  Xiuyu CAI

IPC: H01L29/78 ,  H01L29/06 ,  H01L29/66 ,  H01L29/49 ,  H01L21/768

CPC classification number: H01L29/7856 ,  H01L21/76816 ,  H01L21/76897 ,  H01L29/0657 ,  H01L29/4975 ,  H01L29/6681 ,  H01L2029/7858

Abstract: Tapered source and drain contacts for use in an epitaxial FinFET prevent short circuits and damage to parts of the FinFET during contact processing, thus improving device reliability. The inventive contacts feature tapered sidewalls and a pedestal where electrical contact is made to fins in the source and drain regions. The pedestal also provides greater contact area to the fins, which are augmented by extensions. Raised isolation regions define a valley around the fins. During source/drain contact formation, the valley is lined with a conformal barrier that also covers the fins themselves. The barrier protects underlying local oxide and adjacent isolation regions against gouging while forming the contact. The valley is filled with an amorphous silicon layer that protects the epitaxial fin material from damage during contact formation. A simple tapered structure is used for the gate contact.

Abstract translation: 用于外延FinFET的锥形源极和漏极触点可防止接触处理期间FinFET的短路和损坏，从而提高器件的可靠性。 本发明的触头具有锥形侧壁和与源极和漏极区域中的翅片电接触的基座。 底座还为翅片提供了更大的接触面积，它们通过延伸部分增加。 凸起的隔离区域围绕翅片限定一个谷。 在源极/漏极接触形成期间，谷物衬有也覆盖翅片本身的共形屏障。 当形成接触时，屏障保护底层局部氧化物和相邻隔离区域免受气刨。 该谷填充有非晶硅层，其保护外延翅片材料免于接触形成期间的损坏。 栅极接触使用简单的锥形结构。

公开(公告)号：US20160190304A1

公开(公告)日：2016-06-30

申请号：US14588221

申请日：2014-12-31

Applicant: STMICROELECTRONICS, INC. ,  GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Pierre MORIN ,  Kangguo CHENG ,  Jody FRONHEISER ,  Xiuyu CAI ,  Juntao LI ,  Shogo MOCHIZUKI ,  Ruilong XIE ,  Hong HE ,  Nicolas LOUBET

IPC: H01L29/78 ,  H01L29/66 ,  H01L21/02 ,  H01L29/16 ,  H01L29/06

CPC classification number: H01L29/785 ,  H01L21/823807 ,  H01L21/823821 ,  H01L27/0924 ,  H01L29/0649 ,  H01L29/16 ,  H01L29/66795 ,  H01L29/7849

Abstract: A modified silicon substrate having a substantially defect-free strain relaxed buffer layer of SiGe is suitable for use as a foundation on which to construct a high performance CMOS FinFET device. The substantially defect-free SiGe strain-relaxed buffer layer can be formed by making cuts in, or segmenting, a strained epitaxial film, causing edges of the film segments to experience an elastic strain relaxation. When the segments are small enough, the overall film is relaxed so that the film is substantially without dislocation defects. Once the substantially defect-free strain-relaxed buffer layer is formed, strained channel layers can be grown epitaxially from the relaxed SRB layer. The strained channel layers are then patterned to create fins for a FinFET device. In one embodiment, dual strained channel layers are formed—a tensilely strained layer for NFET devices, and a compressively strained layer for PFET devices.

Abstract translation: 具有基本上无缺陷的SiGe应变松弛缓冲层的改性硅衬底适用于构建高性能CMOS FinFET器件的基础。 可以通过切割或分割应变的外延膜来形成基本上无缺陷的SiGe应变松弛缓冲层，使得薄膜段的边缘经历弹性应变弛豫。 当片段足够小时，整个膜被松弛，使得膜基本上没有位错缺陷。 一旦形成了基本上无缺陷的应变松弛缓冲层，则可以从松弛的SRB层外延生长应变通道层。 然后将应变通道层图案化以产生用于FinFET器件的鳍片。 在一个实施例中，形成双应变通道层 - 用于NFET器件的拉伸应变层，以及用于PFET器件的压缩应变层。

公开(公告)号：US20150333086A1

公开(公告)日：2015-11-19

申请号：US14280998

申请日：2014-05-19

Applicant: STMICROELECTRONICS, INC ,  GLOBALFOUNDRIES Inc. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Qing LIU ,  Xiuyu CAI ,  Ruilong XIE ,  Chun-chen Yeh ,  Kejia Wang ,  Daniel Chanemougame

IPC: H01L27/12 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L21/845 ,  H01L27/1211 ,  H01L29/0649 ,  H01L29/161 ,  H01L29/66795

Abstract: A method for making a semiconductor device may include forming, above a substrate, first and second semiconductor regions laterally adjacent one another and each including a first semiconductor material. The first semiconductor region may have a greater vertical thickness than the second semiconductor region and define a sidewall with the second semiconductor region. The method may further include forming a spacer above the second semiconductor region and adjacent the sidewall, and forming a third semiconductor region above the second semiconductor region and adjacent the spacer, with the second semiconductor region including a second semiconductor material different than the first semiconductor material. The method may also include removing the spacer and portions of the first semiconductor material beneath the spacer, forming a first set of fins from the first semiconductor region, and forming a second set of fins from the second and third semiconductor regions.

Abstract translation: 制造半导体器件的方法可以包括在衬底上方形成彼此横向相邻并且包括第一半导体材料的第一和第二半导体区域。 第一半导体区域可以具有比第二半导体区域更大的垂直厚度并且限定具有第二半导体区域的侧壁。 该方法还可以包括在第二半导体区域的上方形成并邻近侧壁的间隔物，以及在第二半导体区域上方并邻近间隔物形成第三半导体区域，其中第二半导体区域包括与第一半导体材料不同的第二半导体材料 。 该方法还可以包括在间隔物下面移除间隔物和第一半导体材料的部分，从第一半导体区域形成第一组散热片，以及从第二和第三半导体区域形成第二组散热片。