公开(公告)号：US20190088541A1

公开(公告)日：2019-03-21

申请号：US15709956

申请日：2017-09-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Nicholas V. LICAUSI ,  Xunyuan ZHANG

IPC: H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L21/76883 ,  H01L21/32134 ,  H01L21/32135 ,  H01L21/76843 ,  H01L23/5226 ,  H01L23/5283 ,  H01L23/53209 ,  H01L23/53228 ,  H01L23/53252 ,  H01L23/53257 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to fully aligned via structures and methods of manufacture. The structure includes: a plurality of minimum ground rule conductive structures formed in a dielectric material each of which comprises a recessed conductive material therein; at least one conductive structure formed in the dielectric material which is wider than the plurality of minimum ground rule conductive structures; an etch stop layer over a surface of the dielectric layer with openings to expose the conductive material of the least one conductive structure and the recessed conductive material of a selected minimum ground rule conductive structure; and an upper conductive material fully aligned with and in direct electrical contact with the at least one conductive structure and the selected minimum ground rule conductive structure, through the openings of the etch stop layer.

公开(公告)号：US20140353802A1

公开(公告)日：2014-12-04

申请号：US13903802

申请日：2013-05-28

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Nicholas Vincent LICAUSI ,  Errol Todd RYAN ,  Ming HE ,  Moosung M. CHAE ,  Kunaljeet TANWAR ,  Larry ZHAO ,  Christian WITT ,  Ailian ZHAO ,  Sean X. LIN ,  Xunyuan ZHANG

IPC: H01L21/314 ,  H01L21/32 ,  H01L21/308 ,  H01L29/06

CPC classification number: H01L21/314 ,  H01L21/308 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/32 ,  H01L21/76814 ,  H01L21/7682 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L29/06 ,  H01L2221/1047

Abstract: A process is provided for methods of reducing damage to an ultra-low k layer during fabrication. In one aspect, a method includes: providing a cured ultra-low k film containing pores filled with a pore-stuffing material; and modifying an exposed surface of the ultra-low k film to provide a modified layer in the ultra-low k film. In another aspect, a semiconductor device comprising a modified layer on a surface of an ultra-low k film is provided.

Abstract translation: 提供了一种在制造期间减少对超低k层的损伤的方法的方法。 一方面，一种方法包括：提供含有填充有孔填充材料的孔的固化的超低k膜; 以及改变超低k膜的暴露表面以在超低k膜中提供改性层。 在另一方面，提供一种在超低k膜的表面上包含改性层的半导体器件。

公开(公告)号：US20140209563A1

公开(公告)日：2014-07-31

申请号：US13754170

申请日：2013-01-30

Applicant: GLOBALFOUNDRIES, INC.

Inventor： Xunyuan ZHANG ,  Xiuyu CAI

IPC: H05K3/00

CPC classification number: H01L21/3212 ,  C09G1/02 ,  H01L21/283 ,  H01L21/32115 ,  H01L21/7684 ,  H01L21/76888 ,  H01L23/53228 ,  H01L45/1633 ,  H01L2924/0002 ,  H05K3/00 ,  H05K3/26 ,  H05K2201/0376 ,  H05K2203/0346 ,  H01L2924/00

Abstract: Greater planarity is achieved between surfaces of a conductive structure and a layer within which the conductive structure resides. A portion of the conductive structure protruding above the surface of the layer is selectively oxidized, at least in part, to form an oxidized portion. The oxidized portion is then removed, at least partially, to facilitate achieving greater planarity. The protruding portions may optionally be formed by selectively disposing conductive material over the conductive structure, when that the conductive structure is initially recessed below the surface of the layer. A further embodiment includes selectively oxidizing a portion of the conductive structure below the surface of the layer, removing at least some of the oxidized portion so that an upper surface of the conductive structure is below the upper surface of the layer, and planarizing the upper surface of the layer to the upper surface of the conductive structure.

Abstract translation: 在导电结构的表面和导电结构所在的层之间实现更大的平坦度。 突出在层表面之上的导电结构的一部分被至少部分地选择性地氧化以形成氧化部分。 至少部分地去除氧化部分，以便于实现更大的平坦度。 当导电结构最初凹陷在层的表面下方时，可以可选地通过在导电结构上方选择性地设置导电材料来形成突出部分。 另一个实施例包括选择性地将导电结构的一部分氧化在该层的表面之下，去除至少一些氧化部分，使得导电结构的上表面在该层的上表面之下，并平坦化上表面 的层到导电结构的上表面。

公开(公告)号：US20180269150A1

公开(公告)日：2018-09-20

申请号：US15983168

申请日：2018-05-18

Applicant: GLOBALFOUNDRIES INC.

Inventor： Sean Xuan LIN ,  Xunyuan ZHANG ,  Shao Beng LAW ,  James Jay McMahon

IPC: H01L23/522 ,  H01L21/768 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/76816 ,  H01L21/76879 ,  H01L23/53209 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53252 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to metal interconnect structures for super (skip) via integration and methods of manufacture. The structure includes: a first wiring layer with one or more wiring structures; a second wiring layer including an interconnect and wiring structure; and at least one upper wiring layer with one or more via interconnect and wiring structures located above the second wiring layer. The one or more via interconnect and wiring structures partially including a first metal material and remaining portions with a conductive material over the first metal material. A skip via passes through the second wiring layer and extends to the one or more wiring structures of the first wiring layer. The skip via partially includes the metal material and remaining portions of the skip via includes the conductive material over the first metal material.

公开(公告)号：US20170345752A1

公开(公告)日：2017-11-30

申请号：US15168899

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/522 ,  H01L21/285 ,  H01L21/768 ,  H01L21/02 ,  H01L23/532 ,  H01L23/528

CPC classification number: H01L23/5226 ,  H01L21/02244 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/28568 ,  H01L21/768 ,  H01L21/7682 ,  H01L21/7684 ,  H01L21/7685 ,  H01L21/76864 ,  H01L23/5222 ,  H01L23/528 ,  H01L23/53252 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20150130063A1

公开(公告)日：2015-05-14

申请号：US14550531

申请日：2014-11-21

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Kunaljeet TANWAR

IPC: H01L23/532

CPC classification number: H01L23/53238 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76846 ,  H01L21/76855 ,  H01L21/76877 ,  H01L21/76879 ,  H01L23/5329 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming a doped TaN Cu barrier adjacent to a Ru layer of a Cu interconnect structure and the resulting device are provided. Embodiments include forming a cavity in a SiO-based ILD; conformally forming a doped TaN layer in the cavity and over the ILD; conformally forming a Ru layer on the doped TaN layer; depositing Cu over the Ru layer and filling the cavity; planarizing the Cu, Ru layer, and doped TaN layer down to an upper surface of the ILD; forming a dielectric cap over the Cu, Ru layer, and doped TaN layer; and filling spaces formed between the dielectric cap and the doped TaN layer

Abstract translation: 提供了形成与Cu互连结构的Ru层相邻的掺杂TaN Cu势垒的方法和所得到的器件。 实施例包括在SiO基ILD中形成空腔; 在空腔中并在ILD上保形地形成掺杂的TaN层; 在掺杂的TaN层上保形地形成Ru层; 在Ru层上沉积Cu并填充空腔; 将Cu，Ru层和掺杂的TaN层平坦化到ILD的上表面; 在Cu，Ru层和掺杂的TaN层上形成电介质盖; 以及形成在电介质盖和掺杂的TaN层之间的填充空间

公开(公告)号：US20190206682A1

公开(公告)日：2019-07-04

申请号：US15860161

申请日：2018-01-02

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Ruilong XIE ,  Yi QI

IPC: H01L21/033 ,  H01L21/02

CPC classification number: H01L21/0335 ,  H01L21/02532 ,  H01L21/02636 ,  H01L21/0332

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to cut margin structures and methods of manufacture. The method includes: forming a plurality of patterned hardmask stacks containing at least a semiconductor layer and a capping layer; removing a portion of a first patterned hardmask stack and a margin of an adjacent hardmask stack of the plurality of the patterned hardmask stacks; and selectively growing material on the margin of the adjacent hardmask stack.

公开(公告)号：US20180151504A1

公开(公告)日：2018-05-31

申请号：US15875212

申请日：2018-01-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Xunyuan ZHANG ,  Roderick A. AUGUR ,  Hoon KIM

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/528 ,  H01L23/522

CPC classification number: H01L21/7682 ,  H01L21/76883 ,  H01L21/76885 ,  H01L21/76897 ,  H01L23/5221 ,  H01L23/53242 ,  H01L23/53295

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to self-aligned interconnect structures and methods of manufacture. The structure includes an interconnect structure which is self-aligned with an upper level via metallization, and both the interconnect structure and the upper level via metallization are composed of a Pt group material.

公开(公告)号：US20180040555A1

公开(公告)日：2018-02-08

申请号：US15785665

申请日：2017-10-17

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/02 ,  H01L21/768 ,  H01L21/285 ,  H01L23/528

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a barrier layer along a top surface of the semiconductor interconnect device; depositing and annealing a metal interconnect material over a top surface of the barrier layer, wherein the metal interconnect material fills the set of trenches and the set of vias; planarizing a top surface of the intermediate semiconductor interconnect device; exposing a portion of the barrier layer between the set of trenches and the set of vias; and depositing a dielectric cap. Also disclosed is an intermediate device formed by the method.

公开(公告)号：US20170345766A1

公开(公告)日：2017-11-30

申请号：US15168930

申请日：2016-05-31

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Xunyuan ZHANG ,  Frank W. MONT ,  Errol Todd RYAN

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L23/528 ,  H01L23/522 ,  H01L21/285

CPC classification number: H01L23/53252 ,  H01L21/2855 ,  H01L21/28556 ,  H01L21/31111 ,  H01L21/7682 ,  H01L21/76831 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76864 ,  H01L21/76867 ,  H01L21/76877 ,  H01L23/5222 ,  H01L23/5226 ,  H01L23/528 ,  H01L23/5329 ,  H01L23/53295

Abstract: Devices and methods of fabricating integrated circuit devices for forming low resistivity interconnects with improved adhesion are provided. One method includes, for instance: obtaining an intermediate semiconductor interconnect device having a substrate, a cap layer, and a dielectric matrix including a set of trenches and a set of vias; depositing a metal interconnect material directly over and contacting a top surface of the dielectric matrix, wherein the metal interconnect material fills the set of trenches and the set of vias; depositing a barrier layer over a top surface of the device; annealing the barrier layer to diffuse the barrier layer to a bottom surface of the metal interconnect material; planarizing a top surface of the intermediate semiconductor interconnect device; and depositing a dielectric cap over the intermediate semiconductor interconnect device.