公开(公告)号：US20170352619A1

公开(公告)日：2017-12-07

申请号：US15172551

申请日：2016-06-03

Applicant: GLOBALFOUNDRIES INC.

Inventor： Baozhen Li ,  Chih-Chao Yang ,  Keith Kwong Hon Wong

IPC: H01L23/522 ,  H01L23/528 ,  H01L21/768 ,  H01L49/02 ,  H01L23/532 ,  H01L21/02

CPC classification number: H01L23/5223 ,  H01L21/76807 ,  H01L21/76831 ,  H01L21/76877 ,  H01L23/53223 ,  H01L23/53238 ,  H01L23/53266 ,  H01L23/5329 ,  H01L28/60

Abstract: Various embodiments include methods and integrated circuit structures. In some cases, a method of forming an integrated circuit structure can include: forming an opening in a low-k dielectric layer; filling the opening with a high-k dielectric material; patterning the low-k dielectric layer outside of the opening and the high-k dielectric layer to form an interconnect opening within the low-k dielectric layer and a capacitor opening within the high-k dielectric layer; and filling the interconnect opening and the capacitor opening with a metal to form an interconnect in the low-k dielectric layer and a capacitor in the high-k dielectric layer.

公开(公告)号：US09558999B2

公开(公告)日：2017-01-31

申请号：US14025047

申请日：2013-09-12

Applicant: GLOBALFOUNDRIES INC.

Inventor： Juntao Li ,  Chih-Chao Yang ,  Yunpeng Yin

IPC: H01L21/768 ,  H01L21/285 ,  H01L21/288

CPC classification number: H01L21/76885 ,  H01L21/28562 ,  H01L21/288 ,  H01L21/7682 ,  H01L21/76834 ,  H01L21/76844 ,  H01L21/76846 ,  H01L21/76852 ,  H01L21/76879

Abstract: The embodiments of the present invention relate generally to the fabrication of integrated circuits, and more particularly to a structure and method for fabricating a pair of ultra-thin metal wires in an opening using a selective deposition process.

Abstract translation: 本发明的实施例一般涉及集成电路的制造，更具体地涉及一种使用选择性沉积工艺在开口中制造一对超薄金属线的结构和方法。

公开(公告)号：US09202879B2

公开(公告)日：2015-12-01

申请号：US13775988

申请日：2013-02-25

Applicant: GLOBALFOUNDRIES INC.

Inventor： Charles W. Koburger, III ,  Marc A. Bergendahl ,  David V. Horak ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L21/336 ,  H01L29/40 ,  E21B43/30 ,  E21B47/12

CPC classification number: H01L29/401 ,  E21B43/305 ,  E21B47/122 ,  H01L21/823431 ,  H01L21/823456 ,  H01L21/845 ,  H01L27/088 ,  H01L27/0886 ,  H01L27/1211

Abstract: In a replacement gate scheme, after formation of a gate dielectric layer, a work function material layer completely fills a narrow gate trench, while not filling a wide gate trench. A dielectric material layer is deposited and planarized over the work function material layer, and is subsequently recessed to form a dielectric material portion overlying a horizontal portion of the work function material layer within the wide gate trench. The work function material layer is recessed employing the dielectric material portion as a part of an etch mask to form work function material portions. A conductive material is deposited and planarized to form gate conductor portions, and a dielectric material is deposited and planarized to form gate cap dielectrics.

Abstract translation: 在替代栅极方案中，在形成栅极电介质层之后，功函数材料层完全填充窄栅极沟槽，同时不填充宽栅极沟槽。 介电材料层在功函数材料层上沉积并平面化，随后凹入以形成覆盖宽栅极沟槽内的功函数材料层的水平部分的介电材料部分。 使用介电材料部分作为蚀刻掩模的一部分来凹入功函数材料层以形成功函数材料部分。 将导电材料沉积并平坦化以形成栅极导体部分，并且沉积和平坦化介电材料以形成栅极盖电介质。

公开(公告)号：US10177091B2

公开(公告)日：2019-01-08

申请号：US15048114

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andrew H. Simon ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768 ,  H01L21/311 ,  H01L21/02

Abstract: Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

公开(公告)号：US20170243827A1

公开(公告)日：2017-08-24

申请号：US15048114

申请日：2016-02-19

Applicant: GLOBALFOUNDRIES INC.

Inventor： Andrew H. Simon ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L23/528 ,  H01L21/02 ,  H01L21/768 ,  H01L21/311

CPC classification number: H01L23/53238 ,  H01L21/02063 ,  H01L21/02247 ,  H01L21/02252 ,  H01L21/02255 ,  H01L21/31111 ,  H01L21/76802 ,  H01L21/76826 ,  H01L21/76828 ,  H01L21/7684 ,  H01L21/76843 ,  H01L21/76877

Abstract: Aspects of the present disclosure include a method of forming a semiconductor interconnect structure and the interconnect structure. The method includes etching an opening in a first interconnect dielectric material. The method includes performing a nitridation process that converts the surfaces of the opening into nitride residues, and forms a nitrided interconnect dielectric material surface in the opening. The method includes depositing tantalum to create a tantalum layer on the nitrided interconnect dielectric surface region. The method includes depositing copper to fill the opening and planarizing the surface of the first dielectric material.

公开(公告)号：US09627377B2

公开(公告)日：2017-04-18

申请号：US14538401

申请日：2014-11-11

Applicant: GLOBALFOUNDRIES INC.

Inventor： Marc Adam Bergendahl ,  Kangguo Cheng ,  David Vaclav Horak ,  Ali Khakifirooz ,  Shom Ponoth ,  Theodorus Eduardus Standaert ,  Chih-Chao Yang ,  Charles William Koburger, III ,  Xiuyu Cai ,  Ruilong Xie

IPC: H01L27/08 ,  H01L27/088 ,  H01L29/78 ,  H01L29/06 ,  H01L29/66

CPC classification number: H01L27/0886 ,  H01L29/0649 ,  H01L29/6681 ,  H01L29/7855

Abstract: Embodiments of the present invention provide a method of forming semiconductor structure. The method includes forming a set of device features on top of a substrate; forming a first dielectric layer directly on top of the set of device features and on top of the substrate, thereby creating a height profile of the first dielectric layer measured from a top surface of the substrate, the height profile being associated with a pattern of an insulating structure that fully surrounds the set of device features; and forming a second dielectric layer in areas that are defined by the pattern to create the insulating structure. A structure formed by the method is also disclosed.

公开(公告)号：US09385025B2

公开(公告)日：2016-07-05

申请号：US14573268

申请日：2014-12-17

Applicant: GLOBALFOUNDRIES INC.

Inventor： Rajiv V. Joshi ,  Chih-Chao Yang

IPC: H01L23/525 ,  H01L21/768 ,  H01L45/00 ,  H01L27/24 ,  H01L23/532 ,  H01L27/112 ,  H01L23/522

CPC classification number: H01L21/768 ,  H01L23/5226 ,  H01L23/5256 ,  H01L23/53257 ,  H01L27/11206 ,  H01L27/2463 ,  H01L45/04 ,  H01L45/06 ,  H01L45/1206 ,  H01L45/1226 ,  H01L45/1266 ,  H01L45/142 ,  H01L45/143 ,  H01L45/144 ,  H01L45/146 ,  H01L45/148 ,  H01L45/16 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Semiconductor structures are provided containing an electronic fuse (E-fuse) that includes a fuse element and at least one underlying tungsten contact that is used for programming the fuse element. In some embodiments, a pair of neighboring tungsten contacts is used for programming the fuse element. In another embodiment, an overlying conductive region can be used in conjunction with one of the underlying tungsten contacts to program the fuse element. In the disclosed structures, the fuse element is in direct contact with upper surfaces of a pair of underlying tungsten contacts. In one embodiment, the semiconductor structures may include an interconnect level located atop the fuse element. The interconnect level has a plurality of conductive regions embedded therein. In other embodiments, the fuse element is located within an interconnect level that is located atop the tungsten contacts.

公开(公告)号：US09343407B2

公开(公告)日：2016-05-17

申请号：US14664036

申请日：2015-03-20

Applicant: GLOBALFOUNDRIES INC.

Inventor： Fenton Read McFeely ,  Chih-Chao Yang

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528

CPC classification number: H01L23/53238 ,  H01L21/76846 ,  H01L21/76882 ,  H01L23/5226 ,  H01L23/528 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Techniques formation of high purity copper (Cu)-filled lines and vias are provided. In one aspect, a method of fabricating lines and vias filled with high purity copper with is provided. The method includes the following steps. A via is etched in a dielectric. The via is lined with a diffusion barrier. A thin ruthenium (Ru) layer is conformally deposited onto the diffusion barrier. A Cu layer is deposited on the Ru layer by a sputtering process. A reflow anneal is performed to eliminate voids in the lines and vias.

公开(公告)号：US09263388B2

公开(公告)日：2016-02-16

申请号：US14688027

申请日：2015-04-16

Applicant: GLOBALFOUNDRIES INC.

Inventor： Steven J. Holmes ,  David V. Horak ,  Charles W. Koburger, III ,  Shom Ponoth ,  Chih-Chao Yang

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/528 ,  H01L21/768 ,  H01L21/311 ,  H01L23/522 ,  H01L21/44

CPC classification number: H01L23/528 ,  H01L21/31144 ,  H01L21/76807 ,  H01L21/76816 ,  H01L21/76831 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/0001 ,  H01L2924/00

Abstract: A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.