公开(公告)号：US20160163555A1

公开(公告)日：2016-06-09

申请号：US14676097

申请日：2015-04-01

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L21/311 ,  H01L21/8234

CPC classification number: H01L21/823456 ,  H01L21/0337 ,  H01L21/32139 ,  H01L21/823431

Abstract: Methods of forming features having differing pitch spacing and critical dimensions are disclosed herein. One method includes forming an underlying layer of material above a semiconductor substrate. The method further includes forming a masking layer above the underlying layer of material. The masking layer includes features positioned above a first region of the substrate and features positioned above a second region of the substrate. The features have different pitch spacing and critical dimensions. The method further includes performing at least one etching process on the underlying layer of material through the masking layer.

Abstract translation: 本文公开了形成具有不同间距间距和临界尺寸的特征的方法。 一种方法包括在半导体衬底上形成下层材料。 该方法还包括在材料的下层上形成掩模层。 掩模层包括位于衬底的第一区域上方的特征，以及位于衬底的第二区域之上的特征。 这些特征具有不同的间距和关键尺寸。 该方法还包括通过掩模层对材料的下层进行至少一个蚀刻工艺。

公开(公告)号：US20150380405A1

公开(公告)日：2015-12-31

申请号：US14318822

申请日：2014-06-30

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Soon-cheon Seo ,  Linus Jang

IPC: H01L27/088 ,  H01L21/8234 ,  H01L21/027 ,  H01L21/3105 ,  H01L21/306 ,  H01L29/423 ,  H01L21/311

CPC classification number: H01L21/30604 ,  H01L21/0274 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31133 ,  H01L21/31144 ,  H01L21/823412 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/84 ,  H01L27/0886 ,  H01L29/4238 ,  H01L29/66795 ,  H01L29/785

Abstract: After semiconductor material portions and gate structures are formed on a substrate, a dielectric material layer is deposited on the semiconductor material portions and the gate structures. An anisotropic etch is performed on the dielectric material layer to form gate spacers, while a mask layer protects peripheral portions of the semiconductor material portions and the gate structures to avoid unwanted physical exposure of semiconductor surfaces. A selective epitaxy can be performed to form raised active regions on the semiconductor material portions. Formation of semiconductor growth defects during the selective epitaxy is prevented by the dielectric material layer. Alternately, a selective semiconductor deposition process can be performed after formation of dielectric gate spacers on gate structures overlying semiconductor material portions. Semiconductor growth defects can be removed by an etch while a mask layer protects raised active regions on the semiconductor material portions.

Abstract translation: 在衬底上形成半导体材料部分和栅极结构之后，在半导体材料部分和栅极结构上沉积介电材料层。 在电介质材料层上进行各向异性蚀刻以形成栅极间隔物，而掩模层保护半导体材料部分和栅极结构的外围部分以避免半导体表面的不期望的物理暴露。 可以进行选择性外延以在半导体材料部分上形成凸起的有源区。 通过介电材料层可以防止选择性外延期间的半导体生长缺陷的形成。 或者，可以在覆盖半导体材料部分的栅极结构上形成介电栅极间隔物之后执行选择性半导体沉积工艺。 半导体生长缺陷可以通过蚀刻去除，而掩模层保护半导体材料部分上的凸起的有源区。

公开(公告)号：US20150064912A1

公开(公告)日：2015-03-05

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

公开(公告)号：US20140329388A1

公开(公告)日：2014-11-06

申请号：US13874577

申请日：2013-05-01

Applicant: GLOBALFOUNDRIES INC. ,  INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: Disclosed herein are methods of patterning features that have differing widths. In one example, the method includes forming a layer of material above a semiconductor substrate, forming a masking layer above the layer of material, wherein the masking layer is comprised of a first plurality features positioned above a first region of the semiconductor substrate and a second plurality of features positioned above a second region of the semiconductor substrate, wherein the first and second plurality of features have the same pitch spacing and wherein the first and second plurality of features have different widths, and performing at least one etching process on the layer of material through the masking layer.

Abstract translation: 本文公开了具有不同宽度的图案特征的方法。 在一个示例中，该方法包括在半导体衬底之上形成材料层，在材料层之上形成掩模层，其中掩模层由位于半导体衬底的第一区域上方的第一多个特征构成，第二 多个特征位于所述半导体衬底的第二区域之上，其中所述第一和第二多个特征具有相同的间距间距，并且其中所述第一和第二多个特征具有不同的宽度，并且对所述第一和第二多个特征层进行至少一个蚀刻处理 材料通过掩模层。

公开(公告)号：US10283505B2

公开(公告)日：2019-05-07

申请号：US15418996

申请日：2017-01-30

Applicant: GLOBALFOUNDRIES Inc.

Inventor： Wenhui Wang ,  Ryan Ryoung-han Kim ,  Linus Jang ,  Jason Cantone ,  Lei Sun ,  Seowoo Nam

IPC: H01L23/52 ,  H01L27/092 ,  H01L21/8238 ,  H01L29/66 ,  H01L29/06 ,  H01L23/528 ,  H01L21/02 ,  H01L21/321 ,  H01L27/02 ,  H01L29/49

Abstract: Process of using a dummy gate as an interconnection and a method of manufacturing the same are disclosed. Embodiments include forming on a semiconductor substrate dummy gate structures at cell boundaries, each dummy gate structure including a set of sidewall spacers and a cap disposed between the sidewall spacers; removing a first sidewall spacer or at least a portion of a first cap on a first side of a first dummy gate structure and forming a first gate contact trench over the first dummy gate structure; and filling the first gate contact trench with a metal to form a first gate contact.

公开(公告)号：US09466505B2

公开(公告)日：2016-10-11

申请号：US14935767

申请日：2015-11-09

Applicant: GLOBALFOUNDRIES Inc. ,  International Business Machines Corporation

Inventor： Linus Jang ,  Soon-Cheon Seo ,  Ryan O. Jung

IPC: H01L21/311 ,  H01L21/308 ,  H01L21/033 ,  H01L21/3213 ,  H01L21/28 ,  H01L21/8238 ,  H01L21/283 ,  H01L29/66

CPC classification number: H01L21/3085 ,  H01L21/0337 ,  H01L21/28141 ,  H01L21/283 ,  H01L21/3081 ,  H01L21/32139 ,  H01L21/82385 ,  H01L29/6656

Abstract: A method includes forming a layer of material above a semiconductor substrate and performing a first sidewall image transfer process to form a first plurality of spacers and a second plurality of spacers above the layer of material, wherein the first and second pluralities of spacers are positioned above respective first and second regions of the semiconductor substrate and have a same initial width and a same pitch spacing. A masking layer is formed above the layer of material so as to cover the first plurality of spacers and expose the second plurality of spacers, and a first etching process is performed through the masking layer on the exposed second plurality of spacers so as to form a plurality of reduced-width spacers having a width that is less than the initial width, wherein the first plurality of spacers and the plurality of reduced-width spacers define an etch mask.

Abstract translation: 一种方法包括在半导体衬底上形成材料层并执行第一侧壁图像转移工艺以在材料层之上形成第一多个间隔物和第二多个间隔物，其中第一和第二多个间隔物位于 相应的半导体衬底的第一和第二区域，并且具有相同的初始宽度和相同的间距间距。 在材料层的上方形成掩模层，以便覆盖第一多个间隔物并露出第二多个间隔物，并且通过暴露的第二多个间隔物上的掩模层进行第一蚀刻工艺，从而形成 多个宽度窄于所述初始宽度的宽度窄的间隔物，其中所述第一多个间隔物和所述多个减小宽度的间隔物限定蚀刻掩模。

公开(公告)号：US09431264B2

公开(公告)日：2016-08-30

申请号：US14014906

申请日：2013-08-30

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Linus Jang ,  Young Joon Moon ,  Ryan Ryoung Han Kim

IPC: H01L21/308 ,  H01L21/033 ,  H01L21/8234 ,  H01L21/311 ,  H01L21/3213 ,  H01L21/28

CPC classification number: H01L21/3086 ,  H01L21/0337 ,  H01L21/28132 ,  H01L21/31144 ,  H01L21/32139 ,  H01L21/823437 ,  H01L21/823456

Abstract: Methods of forming integrated circuits and multiple CD SADP processes are provided that include providing a patternable structure including a first hard mask layer and a first patternable layer underlying the first hard mask layer. Mandrels are provided over the first hard mask layer. Sidewall spacers are formed adjacent sidewalls of the mandrels. The mandrels are removed, with the sidewall spacers remaining and defining gaps therebetween. The first hard mask layer is etched through the gaps to form a first patterned hard mask feature and a second patterned hard mask feature. A critical dimension of the first patterned hard mask feature is selectively modified to form a biased hard mask feature. A space is defined between sidewalls of the biased hard mask feature and the second patterned hard mask feature. The first patternable layer is etched through exposed material in the space.

Abstract translation: 提供形成集成电路和多个CD SADP工艺的方法，其包括提供包括第一硬掩模层和第一硬掩模层下面的第一可图案层的可图案结构。 在第一硬掩模层上提供心轴。 侧壁间隔件形成在心轴的相邻侧壁处。 去除心轴，其中侧壁间隔物保留并且在它们之间限定间隙。 通过间隙蚀刻第一硬掩模层以形成第一图案化硬掩模特征和第二图案化硬掩模特征。 选择性地修改第一图案化硬掩模特征的临界尺寸以形成偏置的硬掩模特征。 在偏置的硬掩模特征的侧壁和第二图案化硬掩模特征之间限定空间。 第一可图案层通过空间中的暴露材料进行蚀刻。

公开(公告)号：US20160172467A1

公开(公告)日：2016-06-16

申请号：US15062465

申请日：2016-03-07

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/8234 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/02164 ,  H01L21/2018 ,  H01L21/28238 ,  H01L21/3065 ,  H01L21/31053 ,  H01L21/31111 ,  H01L21/31116 ,  H01L21/31144 ,  H01L21/823425 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L21/823481 ,  H01L21/845 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/41783 ,  H01L29/41791 ,  H01L29/4966 ,  H01L29/51 ,  H01L29/6656 ,  H01L29/66575 ,  H01L29/66795 ,  H01L29/7851 ,  H01L29/7855 ,  H01L2029/7858

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150357434A1

公开(公告)日：2015-12-10

申请号：US14827510

申请日：2015-08-17

Applicant: International Business Machines Corporation ,  GLOBALFOUNDRIES Inc.

Inventor： Linus Jang ,  Sivananda K. Kanakasabapathy ,  Sanjay C. Mehta ,  Soon-Cheon Seo ,  Raghavasimhan Sreenivasan

IPC: H01L29/66 ,  H01L21/3065 ,  H01L21/283

CPC classification number: H01L29/66545 ,  H01L21/283 ,  H01L21/3065 ,  H01L21/31144 ,  H01L21/823431 ,  H01L21/823437 ,  H01L21/823468 ,  H01L29/6656 ,  H01L29/66795

Abstract: A method of fabricating a semiconductor device includes forming at least one semiconductor fin on a semiconductor substrate. A plurality of gate formation layers is formed on an etch stop layer disposed on the fin. The plurality of gate formation layers include a dummy gate layer formed from a dielectric material. The plurality of gate formation layers is patterned to form a plurality of dummy gate elements on the etch stop layer. Each dummy gate element is formed from the dielectric material. A spacer layer formed on the dummy gate elements is etched to form a spacer on each sidewall of dummy gate elements. A portion of the etch stop layer located between each dummy gate element is etched to expose a portion the semiconductor fin. A semiconductor material is epitaxially grown from the exposed portion of the semiconductor fin to form source/drain regions.

公开(公告)号：US20150318181A1

公开(公告)日：2015-11-05

申请号：US14267959

申请日：2014-05-02

Applicant: GLOBALFOUNDRIES, Inc.

Inventor： Jason Richard Cantone ,  Linus Jang ,  Ryan Ryoung-Han Kim

IPC: H01L21/308 ,  H01L29/66

CPC classification number: H01L29/66795 ,  H01L21/3086 ,  H01L21/823431

Abstract: Methods for fabricating integrated circuits and for forming masks for fabricating integrated circuits are provided. An exemplary method for fabricating an integrated circuit includes providing a patternable structure having first and second regions and including upper and lower mandrel layers. The method etches upper mandrels from the upper mandrel layer in the first and second regions. The method includes forming first upper spacer structures having a first width adjacent upper mandrels in the first region and forming second upper spacer structures having a second width not equal to the first width adjacent upper mandrels in the second region. The method etches the lower mandrel layer using the first and second upper spacer structures as an etch mask to form lower mandrels. Further, the method includes forming spacers adjacent the lower mandrels and etching a material using the spacers as an etch mask to form variably spaced features.

Abstract translation: 提供了制造集成电路和形成用于制造集成电路的掩模的方法。 一种用于制造集成电路的示例性方法包括提供具有第一和第二区域并且包括上部和下部心轴层的可图案化结构。 该方法在第一和第二区域中从上心轴层蚀刻上心轴。 该方法包括形成在第一区域中具有与上心轴相邻的第一宽度的第一上间隔结构，并且形成第二上间隔结构，其具有不等于第二区中相邻上心轴的第一宽度的第二宽度。 该方法使用第一和第二上间隔结构蚀刻下心轴层作为蚀刻掩模以形成下心轴。 此外，该方法包括形成邻近下心轴的间隔物，并使用间隔物蚀刻材料作为蚀刻掩模以形成可变间隔的特征。