公开(公告)号：US20210028349A1

公开(公告)日：2021-01-28

申请号：US16521172

申请日：2019-07-24

Applicant: Globalfoundries Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Benfu Lin ,  Chim Seng Seet

IPC: H01L43/02 ,  G11C11/16 ,  H01L27/22 ,  H01L43/10 ,  H01L43/12

Abstract: Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a contact overlying a substrate, and a bottom electrode overlying the contact. The bottom electrode is in electrical communication with the contact, and the bottom electrode has a bottom electrode upper surface with a bottom electrode upper surface area. A magnetic tunnel junction memory cell overlies the bottom electrode and is in electrical communication with the bottom electrode. The magnetic tunnel junction memory cell has an MTJ bottom surface with an MTJ bottom surface area that is greater than the bottom electrode surface area.

公开(公告)号：US09997562B1

公开(公告)日：2018-06-12

申请号：US15458944

申请日：2017-03-14

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lei Wang ,  Benfu Lin ,  Chim Seng Seet ,  Kai Hung Alex See

IPC: H01L21/70 ,  H01L27/22 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L27/222 ,  H01L43/02 ,  H01L43/12

Abstract: A method of forming a semiconductor device is disclosed. The method includes providing a substrate comprising a circuit component formed on a substrate surface. Back-end-of-line (BEOL) processing is performed to form a plurality of inter-level dielectric (ILD) layers over the substrate. A storage unit in the memory region of the via level of an ILD level. A cell dielectric layer is formed over the storage unit. The cell dielectric layer comprises a step structure created by an elevated topography of the memory region relative to the non-memory region of the via level. The elevated topography is defined by the storage unit. Chemical mechanical polishing (CMP) process is performed on the cell dielectric layer to remove the step structure of the cell dielectric layer and form a planar cell dielectric top surface extending uniformly across the memory region and the non-memory region of the via level.

公开(公告)号：US09511474B2

公开(公告)日：2016-12-06

申请号：US15005029

申请日：2016-01-25

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wei Lu ,  Alex See

IPC: B24B49/00 ,  B24B37/005 ,  B24B37/32

CPC classification number: B24B49/00 ,  B24B37/005 ,  B24B37/32

Abstract: A CMP structure for CMP processing and a method of making a device using the same are presented. The apparatus comprises a polishing pad on a platen table; a head assembly for holding a wafer against the polishing pad, wherein the head assembly includes the retaining ring; a sensor for sensing the step height between the retaining ring and its membrane and a controller for adjusting the movement of the retaining ring based on the step height between the retaining ring and its membrane to ensure the step height remains at a fixed value as the retaining ring wears out.

Abstract translation: 提出了一种用于CMP处理的CMP结构和使用其的装置的制造方法。 该装置包括在台板上的抛光垫; 用于将晶片保持在抛光垫上的头组件，其中所述头组件包括所述保持环; 用于感测保持环和其膜之间的台阶高度的传感器以及用于基于保持环与其膜之间的台阶高度来调整保持环的移动的控制器，以确保台阶高度保持在固定值作为保持 戒指磨损了。

公开(公告)号：US12284924B2

公开(公告)日：2025-04-22

申请号：US17697974

申请日：2022-03-18

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Lup San Leong ,  Juan Boon Tan ,  Benfu Lin ,  Yi Jiang

IPC: H10N70/00 ,  H10B63/00

Abstract: According to various embodiments, there may be provided an interposer. The interposer including: a substrate; a dielectric layer disposed on the substrate; a via disposed entirely within the dielectric layer; a resistive film layer disposed to line the via; a metal interconnect disposed in the resistive layer lined via; and a plurality of metal lines disposed in the dielectric layer, the plurality of metal lines including a first metal line connected to the metal interconnect, a second metal line connected to the resistive film layer at a first point, and a third metal line connected to the resistive film layer at a second point.

公开(公告)号：US11742283B2

公开(公告)日：2023-08-29

申请号：US17139117

申请日：2020-12-31

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Kah Wee Gan ,  Benfu Lin ,  Yun Ling Tan

IPC: H01L23/522 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80 ,  H01L49/02

CPC classification number: H01L23/5228 ,  H01L28/20 ,  H10B61/00 ,  H10N50/01 ,  H10N50/80

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to an integrated thin film resistor with a memory device and methods of manufacture. The structure includes a memory device in back end of line (BEOL) materials and a thin film resistor located in the BEOL materials. The thin film resistor includes electrical resistive material, and an insulator material over the electrical resistive material is thicker than insulator material over the memory device.

公开(公告)号：US11641789B2

公开(公告)日：2023-05-02

申请号：US17355260

申请日：2021-06-23

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Yi Jiang ,  Benfu Lin ,  Lup San Leong ,  Curtis Chun-I Hsieh ,  Wanbing Yi ,  Juan Boon Tan

IPC: H10N70/00 ,  H01L45/00 ,  H01L27/24

Abstract: According to various embodiments, there is provided a memory cell. The memory cell may include a transistor, a dielectric member, an electrode and a contact member. The dielectric member may be disposed over the transistor. The electrode may be disposed over the dielectric member. The contact member has a first end and a second end opposite to the first end. The first end is disposed towards the transistor, and the second end is disposed towards the dielectric member. The contact member has a side surface extending from the first end to the second end. The second end may have a recessed end surface that has a section that slopes towards the side surface so as to form a tip with the side surface at the second end. The dielectric member may be disposed over the second end of the contact member and may include at least a portion disposed over the tip.

公开(公告)号：US11610837B2

公开(公告)日：2023-03-21

申请号：US17027661

申请日：2020-09-21

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Xuesong Rao ,  Benfu Lin ,  Bo Li ,  Chengang Feng ,  Yudi Setiawan ,  Yun Ling Tan

IPC: H01L23/522 ,  H01L23/532 ,  H01L21/768

Abstract: A semiconductor device is provided, which includes a dielectric layer and a via structure. The dielectric layer is arranged over a substrate. The via structure is arranged in the dielectric layer, the via structure having a peripheral portion and a central portion. The peripheral portion of the via structure has a height that is greater than that of the central portion.

公开(公告)号：US10693054B2

公开(公告)日：2020-06-23

申请号：US16046648

申请日：2018-07-26

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Danny Pak-Chum Shum ,  Wanbing Yi ,  Curtis Chun-I Hsieh ,  Yi Jiang ,  Juan Boon Tan ,  Benfu Lin

IPC: H01L27/00 ,  H01L43/02 ,  H01L43/12 ,  H01L27/22

Abstract: A method of forming a memory cell with a high aspect ratio metal via formed underneath a metal tunnel junction (MTJ) and the resulting device are provided. Embodiments include a device having a metal via formed underneath a metal tunnel junction (MTJ) in a memory cell, and the metal via has an aspect ratio smaller than 2.

公开(公告)号：US09520371B2

公开(公告)日：2016-12-13

申请号：US14525154

申请日：2014-10-27

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Wanbing Yi ,  Wei Lu ,  Alex See ,  Juan Boon Tan

IPC: H01L23/00 ,  H01L21/3105 ,  H01L21/768 ,  H01L23/522 ,  H01L23/528 ,  H01L23/31 ,  H01L23/532

CPC classification number: H01L24/05 ,  H01L21/31051 ,  H01L21/76807 ,  H01L21/76877 ,  H01L23/3114 ,  H01L23/3192 ,  H01L23/53214 ,  H01L23/53228 ,  H01L23/53295 ,  H01L24/02 ,  H01L24/03 ,  H01L24/48 ,  H01L24/85 ,  H01L24/94 ,  H01L2224/02166 ,  H01L2224/023 ,  H01L2224/0345 ,  H01L2224/03462 ,  H01L2224/03614 ,  H01L2224/03616 ,  H01L2224/0391 ,  H01L2224/04042 ,  H01L2224/05025 ,  H01L2224/05546 ,  H01L2224/05567 ,  H01L2224/05573 ,  H01L2224/05624 ,  H01L2224/05647 ,  H01L2224/48247 ,  H01L2224/94 ,  H01L2924/00014 ,  H01L2924/06 ,  H01L2924/07025 ,  H01L2924/3512 ,  H01L2924/35121 ,  H01L2224/03 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: Devices and methods for forming a device are presented. The method includes providing a substrate having circuit component and a dielectric layer over the substrate. The dielectric layer includes a plurality of inter level dielectric (ILD) layers and the uppermost dielectric layer includes at least one interconnect. A pad dielectric layer is provided over the uppermost ILD layer. A pad interconnect for receiving a wire bond is formed in the pad dielectric layer. The pad interconnect is coupled to the at least one interconnect of the uppermost ILD layer. A top surface of the pad dielectric layer is substantially coplanar with a top surface of the pad interconnect. A passivation layer is formed over the pad dielectric layer.

Abstract translation: 提出了用于形成装置的装置和方法。 该方法包括在衬底上提供具有电路部件和电介质层的衬底。 电介质层包括多个层间介电层（ILD）层，最上面的介电层包括至少一个互连。 衬垫介电层设置在最上面的ILD层之上。 在焊盘介电层中形成用于接收引线接合的焊盘互连。 焊盘互连耦合到最上面的ILD层的至少一个互连。 焊盘介电层的顶表面与焊盘互连的顶表面基本共面。 在焊盘介电层上形成钝化层。

公开(公告)号：US09437547B2

公开(公告)日：2016-09-06

申请号：US15063526

申请日：2016-03-08

Applicant: GLOBALFOUNDRIES Singapore Pte. Ltd.

Inventor： Benfu Lin ,  Hong Yu ,  Lup San Leong ,  Alex See ,  Wei Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/535 ,  H01L23/528 ,  H01L23/532

CPC classification number: H01L23/535 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/528 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A device and methods for forming a device are disclosed. A substrate is provided and a TSV is formed in the substrate through a top surface of the substrate. The TSV and top surface of the substrate is lined with an insulation stack having a first insulation layer, a polish stop layer and a second insulation layer. A conductive layer is formed on the substrate. The TSV is filled with conductive material of the conductive layer. The substrate is planarized to remove excess conductive material of the conductive layer. The planarizing stops on the polish stop layer to form a planar top surface.