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    DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE
    11.
    发明申请
    DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE 有权

    公开(公告)号：US20230050485A1

    公开(公告)日：2023-02-16

    申请号：US17974880

    申请日：2022-10-27

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Edward MACROBBIE

    IPC: H01L23/482 ,  H01L29/778 ,  H01L29/20

    Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

    DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE
    12.
    发明申请
    DEVICE TOPOLOGY FOR LATERAL POWER TRANSISTORS WITH LOW COMMON SOURCE INDUCTANCE 有权

    公开(公告)号：US20220139810A1

    公开(公告)日：2022-05-05

    申请号：US17117449

    申请日：2020-12-10

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Edward MACROBBIE

    IPC: H01L23/482 ,  H01L29/20 ,  H01L29/778

    Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

    HIGH CURRENT LATERAL GaN TRANSISTORS WITH SCALABLE TOPOLOGY AND GATE DRIVE PHASE EQUALIZATION
    13.
    发明申请
    HIGH CURRENT LATERAL GaN TRANSISTORS WITH SCALABLE TOPOLOGY AND GATE DRIVE PHASE EQUALIZATION 审中-公开

    公开(公告)号：US20190081623A1

    公开(公告)日：2019-03-14

    申请号：US15704458

    申请日：2017-09-14

    Applicant: GaN Systems Inc.

    Inventor： Ahmad MIZAN ,  Greg P. KLOWAK ,  Xiaodong CUI

    IPC: H03K17/081 ,  H01L29/20 ,  H01L29/205 ,  H01L29/778 ,  H01L29/06 ,  H01L23/528 ,  H01L23/522

    Abstract: Large area, high current, lateral GaN power transistors are implemented using an on-chip interconnect topology wherein the transistor is arranged as an array of sections, each section comprising a set of transistor islands; gate and source buses that form each gate drive loop have substantially the same track widths; the source bus runs over or under the gate bus, and the tracks are inductively coupled to provide flux cancellation in the gate drive loop, thereby reducing parasitic inductances. The gate delay in each gate drive loop is reduced, minimizing the gate drive phase difference across the transistor. An overlying current redistribution layer preferably has a track width no greater than that of the underlying source and drain buses, for efficient coupling. This topology provides improved scalability, enabling fabrication of multi-section, large scale, high current lateral GaN transistors with reduced gate drive loop inductance, for improved operational stability.

    DISTRIBUTED DRIVER CIRCUITRY INTEGRATED WITH GaN POWER TRANSISTORS
    15.
    发明申请
    DISTRIBUTED DRIVER CIRCUITRY INTEGRATED WITH GaN POWER TRANSISTORS 有权
    分布式驱动电路与GaN功率晶体管集成

    公开(公告)号：US20160301408A1

    公开(公告)日：2016-10-13

    申请号：US15091867

    申请日：2016-04-06

    Applicant: GaN Systems Inc.

    Inventor： John ROBERTS ,  Ahmad MIZAN

    IPC: H03K17/687 ,  H01L29/20

    CPC classification number: H03K17/162 ,  H01L29/2003 ,  H01L29/402 ,  H01L29/41758 ,  H03K17/168 ,  H03K17/6877

    Abstract: Power switching systems are disclosed comprising driver circuitry for enhancement-mode (E-Mode) GaN power transistors with low threshold voltage. Preferably, a GaN power switch (D3) comprises an E-Mode high electron mobility transistor (HEMT) with a monolithically integrated GaN driver. D3 is partitioned into sections. At least the pull-down and, optionally, the pull-up driver circuitry is similarly partitioned as a plurality of driver elements, each driving a respective section of D3. Each driver element is placed in proximity to a respective section of D3, reducing interconnect track length and loop inductance. In preferred embodiments, the layout of GaN transistor switch and the driver elements, dimensions and routing of the interconnect tracks are selected to further reduce loop inductance and optimize performance. Distributed driver circuitry integrated on-chip with one or more high power E-Mode GaN switches allows closer coupling of the driver circuitry and the GaN switches to reduce effects of parasitic inductances.

    Abstract translation: 公开了包括具有低阈值电压的增强型（E模））GaN功率晶体管的驱动电路的电源开关系统。 优选地，GaN功率开关（D3）包括具有单片集成GaN驱动器的E模式高电子迁移率晶体管（HEMT）。 D3被划分为几个部分。 至少下拉和可选地，上拉驱动器电路被类似地划分为多个驱动器元件，每个驱动器元件驱动D3的相应部分。 每个驱动器元件放置在D3的相应部分附近，减少了互连轨道长度和环路电感。 在优选实施例中，选择GaN晶体管开关的布局和驱动元件，互连轨道的尺寸和布线，以进一步降低环路电感并优化性能。 集成片上与一个或多个高功率E-Mode GaN开关的分布式驱动器电路允许驱动电路和GaN开关的更紧密耦合，以减少寄生电感的影响。

    EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS
    17.
    发明申请
    EMBEDDED PACKAGING FOR DEVICES AND SYSTEMS COMPRISING LATERAL GaN POWER TRANSISTORS 有权
    嵌入式封装用于包含侧向GaN功率晶体管的器件和系统

    公开(公告)号：US20160240471A1

    公开(公告)日：2016-08-18

    申请号：US15027012

    申请日：2015-04-15

    Applicant: GaN Systems Inc.

    Inventor： Greg P. KLOWAK ,  Ahmad MIZAN ,  John ROBERTS

    IPC: H01L23/498 ,  H01L23/522 ,  H01L29/20 ,  H01L23/532 ,  H01L29/78 ,  H01L23/482

    CPC classification number: H01L23/49844 ,  H01L23/3107 ,  H01L23/4824 ,  H01L23/5226 ,  H01L23/53228 ,  H01L24/19 ,  H01L24/20 ,  H01L29/2003 ,  H01L29/778 ,  H01L29/78 ,  H01L2224/04105 ,  H01L2224/18 ,  H01L2224/2518 ,  H01L2224/82

    Abstract: Embedded packaging for devices and systems comprising lateral GaN power transistors is disclosed. The packaging assembly is suitable for large area, high power GaN transistors and comprises an assembly of a GaN power transistor and package components comprising a three level interconnect structure. In preferred embodiments, the three level interconnect structure comprises an on-chip metal layer, a copper redistribution layer and package metal layers, in which there is a graduated or tapered contact area sizing through the three levels for dividing/applying current on-chip and combining/collecting current off-chip, with distributed contacts over the active area of the GaN power device. This embedded packaging assembly provides a low inductance, low resistance interconnect structure suitable for devices and systems comprising large area, high power GaN transistors for high voltage/high current applications.

    Abstract translation: 公开了包括横向GaN功率晶体管的器件和系统的嵌入式封装。 包装组件适用于大面积高功率GaN晶体管，并且包括GaN功率晶体管和包括三级互连结构的封装组件的组件。 在优选实施例中，三电平互连结构包括片上金属层，铜再分布层和封装金属层，其中存在通过三个级别分级/施加电流片上的刻度或锥形接触面积， 在GaN功率器件的有源区域上结合/收集芯片外的电流与分布式触点。 该嵌入式封装组件提供适合于用于高电压/高电流应用的大面积高功率GaN晶体管的器件和系统的低电感，低电阻互连结构。

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