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162 条记录 (耗时 0.027 秒)

    Metal/dielectric laminate with electrodes and process thereof
    12.
    发明授权
    Metal/dielectric laminate with electrodes and process thereof 失效
    具有电极的金属/电介质层压板及其工艺

    公开(公告)号：US06509687B1

    公开(公告)日：2003-01-21

    申请号：US09450530

    申请日：1999-11-30

    申请人： Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

    发明人： Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

    IPC分类号： H01J2964

    CPC分类号： H01J29/467 ,  H01J31/127

    摘要： The present invention relates generally to a new electrode forming metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

    摘要翻译： 本发明一般涉及具有通孔的新型电极形成金属/磁陶瓷层压体及其工艺。 更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。 本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。

    Method of protecting a non-planar feature using compressive pads and apparatus thereof
    13.
    发明授权
    Method of protecting a non-planar feature using compressive pads and apparatus thereof 失效
    使用压缩垫保护非平面特征的方法及其装置

    公开(公告)号：US06179951B2

    公开(公告)日：2001-01-30

    申请号：US09263965

    申请日：1999-03-05

    申请人： Govindarajan Natarajan ,  John U. Knickerbocker ,  Suresh D. Kadakia ,  Abubaker S. Shagan

    发明人： Govindarajan Natarajan ,  John U. Knickerbocker ,  Suresh D. Kadakia ,  Abubaker S. Shagan

    IPC分类号： B32B3120

    CPC分类号： B32B37/0023 ,  B32B37/26 ,  B32B2315/02 ,  H01L21/4857

    摘要： The present invention relates generally to a new apparatus and method for forming non-planar surfaces in substrates. More particularly, the invention encompasses an apparatus and a method for fabricating non-planar surfaces in semiconductor substrates wherein at least one zero compression set pad, such as a closed cell porous pad in combination with at least one elastic pad is placed over the non-planar surface prior to lamination and is caused to conform to the contour of the non-planar surface, thus preventing collapse of, or damage to, the non-planar features, such as, shelves or corners during the lamination process. After the lamination process, the zero compression set pad are conveniently removed from the non-planar surface area without causing any damage to the non-planar surface features, such as, shelves or corners or having any paste pull-outs. These zero compression set pads can be reused multiple number of times to form these MLC cavity substrates or similar other structures or features.

    摘要翻译： 本发明一般涉及用于在基片中形成非平面表面的新装置和方法。 更具体地说，本发明包括一种用于在半导体衬底中制造非平面表面的装置和方法，其中至少一个零压缩固定衬垫，例如与至少一个弹性衬垫组合的闭孔多孔垫， 平坦表面，并且使其符合非平面表面的轮廓，从而防止在层压过程期间非平面特征（例如，搁板或角部）的塌陷或损坏。 在层压过程之后，零压缩固定垫可以方便地从非平面表面区域移除，而不会对非平面表面特征（例如，搁板或角落）或具有任何糊状物拉出造成任何损坏。 这些零压缩设定焊盘可以重复使用多次以形成这些MLC腔体衬底或类似的其他结构或特征。

    Decoupling capacitor method and structure using metal based carrier
    16.
    发明授权
    Decoupling capacitor method and structure using metal based carrier 有权
    使用金属载体去耦电容器的方法和结构

    公开(公告)号：US06461493B1

    公开(公告)日：2002-10-08

    申请号：US09472136

    申请日：1999-12-23

    申请人： Mukta S. Farooq ,  Shaji Farooq ,  John U. Knickerbocker ,  Robert A. Rita ,  Srinivasa N. Reddy

    发明人： Mukta S. Farooq ,  Shaji Farooq ,  John U. Knickerbocker ,  Robert A. Rita ,  Srinivasa N. Reddy

    IPC分类号： C25D502

    CPC分类号： H05K3/445 ,  H01G4/10 ,  H05K1/053 ,  H05K1/162 ,  H05K3/4069 ,  H05K2201/09554 ,  H05K2203/0315 ,  H05K2203/1142

    摘要： A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.

    摘要翻译： 一种使用金属载体制造结构并形成双电容器结构的方法。 该工艺包括形成通过金属载体的第一通孔，在金属载体周围形成电介质层，并在第一通孔内部形成介电层，形成穿过电介质层和金属载体的第二通孔，并填充至少一个通孔 孔与导电材料。 在一个优选实施例中，该方法还包括在形成电介质层之前通过金属载体形成第三通孔，其中介电层围绕金属载体形成在第一通孔的内部，以及在第三通孔的内部。 第一通孔，第二通孔和第三通孔均填充有导电材料。 在一个优选实施例中，电介质层包括与底表面相对的顶表面，并且在介电层的顶表面和底表面中的至少一个上形成电极。

    Structure for a thin film multilayer capacitor
    17.
    发明授权
    Structure for a thin film multilayer capacitor 失效
    薄膜多层电容器的结构

    公开(公告)号：US6023407A

    公开(公告)日：2000-02-08

    申请号：US31235

    申请日：1998-02-26

    申请人： Mukta S. Farooq ,  Shaji Farooq ,  Harvey C. Hamel ,  John U. Knickerbocker ,  Robert A. Rita ,  Herbert I. Stoller

    发明人： Mukta S. Farooq ,  Shaji Farooq ,  Harvey C. Hamel ,  John U. Knickerbocker ,  Robert A. Rita ,  Herbert I. Stoller

    IPC分类号： H01L27/04 ,  H01G4/30 ,  H01G4/33 ,  H01L21/02 ,  H01L21/822 ,  H01G4/005 ,  H01G4/228

    CPC分类号： H01L28/40 ,  H01G4/306 ,  Y10T29/435

    摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

    摘要翻译： 提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10μm的厚的第一金属层沉积在衬底上 然后施加剩余的薄膜，包括电介质膜和第二金属层。 第一金属层包括Pt或其它电极金属，或Pt，Cr和Cu金属的组合以及扩散阻挡层。 另外的Ti层可以用于附着增强。 对于Cr层，第一金属层的厚度约为：200A; Cu层为0.5-10μm; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。

    Method for a thin film multilayer capacitor
    20.
    发明授权
    Method for a thin film multilayer capacitor 失效
    薄膜多层电容器的方法

    公开(公告)号：US06216324B1

    公开(公告)日：2001-04-17

    申请号：US09382536

    申请日：1999-08-25

    申请人： Mukta S. Farooq ,  Shaji Farooq ,  Harvey C. Hamel ,  John U. Knickerbocker ,  Robert A. Rita ,  Herbert I. Stoller

    发明人： Mukta S. Farooq ,  Shaji Farooq ,  Harvey C. Hamel ,  John U. Knickerbocker ,  Robert A. Rita ,  Herbert I. Stoller

    IPC分类号： H01G4002

    CPC分类号： H01L28/40 ,  H01G4/306 ,  Y10T29/435

    摘要： An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.

    摘要翻译： 提出了一种电子部件结构，其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑，空隙或起伏引起的上覆薄膜区域中的致命电短路，厚度为0.5-10毫米的厚的第一金属层沉积在衬底上，衬底上沉积 然后施加包括电介质膜和第二金属层的剩余薄膜。 第一金属层由Pt或其他电极金属或Pt，Cr和Cu金属的组合以及扩散阻挡层组成。 另外的Ti层可以用于附着增强。 对于Cr层，第一金属层的厚度约为：200A; 铜层为0.5-10毫米; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。