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1.
公开(公告)号:US06461493B1
公开(公告)日:2002-10-08
申请号:US09472136
申请日:1999-12-23
IPC分类号: C25D502
CPC分类号: H05K3/445 , H01G4/10 , H05K1/053 , H05K1/162 , H05K3/4069 , H05K2201/09554 , H05K2203/0315 , H05K2203/1142
摘要: A process for fabricating a structure using a metal carrier and forming a double capacitor structure. The process comprises forming a first via hole through the metal carrier, forming a dielectric layer around the metal carrier and inside the first via hole, forming a second via hole through the dielectric layer and the metal carrier, and filling at least one of the via holes with conductive material. In one preferred embodiment, the process further comprises forming a third via hole through the metal carrier before the forming of a dielectric layer, wherein the dielectric layer is formed around the metal carrier, inside the first via hole, and inside the third via hole. The first via hole, the second via hole, and the third via hole are all filled with a conductive material. In one preferred embodiment, the dielectric layer comprises a top surface opposed to a bottom surface, and electrodes are formed on at least one of the top surface and the bottom surface of the dielectric layer.
摘要翻译: 一种使用金属载体制造结构并形成双电容器结构的方法。 该工艺包括形成通过金属载体的第一通孔,在金属载体周围形成电介质层,并在第一通孔内部形成介电层,形成穿过电介质层和金属载体的第二通孔,并填充至少一个通孔 孔与导电材料。 在一个优选实施例中,该方法还包括在形成电介质层之前通过金属载体形成第三通孔,其中介电层围绕金属载体形成在第一通孔的内部,以及在第三通孔的内部。 第一通孔,第二通孔和第三通孔均填充有导电材料。 在一个优选实施例中,电介质层包括与底表面相对的顶表面,并且在介电层的顶表面和底表面中的至少一个上形成电极。
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公开(公告)号:US6023407A
公开(公告)日:2000-02-08
申请号:US31235
申请日:1998-02-26
申请人: Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人: Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
CPC分类号: H01L28/40 , H01G4/306 , Y10T29/435
摘要: An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 .mu.m thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer includes of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 .mu.m for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译: 提出了一种电子部件结构,其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑,空隙或起伏引起的上覆薄膜区域中的致命电短路,厚度为0.5-10μm的厚的第一金属层沉积在衬底上 然后施加剩余的薄膜,包括电介质膜和第二金属层。 第一金属层包括Pt或其它电极金属,或Pt,Cr和Cu金属的组合以及扩散阻挡层。 另外的Ti层可以用于附着增强。 对于Cr层,第一金属层的厚度约为:200A; Cu层为0.5-10μm; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。
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公开(公告)号:US06216324B1
公开(公告)日:2001-04-17
申请号:US09382536
申请日:1999-08-25
申请人: Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
发明人: Mukta S. Farooq , Shaji Farooq , Harvey C. Hamel , John U. Knickerbocker , Robert A. Rita , Herbert I. Stoller
IPC分类号: H01G4002
CPC分类号: H01L28/40 , H01G4/306 , Y10T29/435
摘要: An electronic component structure is proposed, wherein an interposer thin film capacitor structure is employed between an active electronic component and a multilayer circuit card. A method for making the interposer thin film capacitor is also proposed. In order to eliminate fatal electrical shorts in the overlying thin film regions that arise from pits, voids, or undulations on the substrate surface, a thick first metal layer, on the order of 0.5-10 mm thick, is deposited on the substrate upon which the remaining thin films, including a dielectric film and second metal layer, are then applied. The first metal layer is comprised of Pt or other electrode metal, or a combination of Pt, Cr, and Cu metals, and a diffusion barrier layer. Additional Ti layers may be employed for adhesion enhancement. The thickness of the first metal layers are approximately: 200 A for the Cr layer; 0.5-10 mm for the Cu layer; 1000 A-5000 A for the diffusion barrier; and 100 A-2500 A for a Pt layer.
摘要翻译: 提出了一种电子部件结构,其中在有源电子部件和多层电路卡之间采用中介层薄膜电容器结构。 还提出了一种用于制造中介层薄膜电容器的方法。 为了消除由衬底表面上的凹坑,空隙或起伏引起的上覆薄膜区域中的致命电短路,厚度为0.5-10毫米的厚的第一金属层沉积在衬底上,衬底上沉积 然后施加包括电介质膜和第二金属层的剩余薄膜。 第一金属层由Pt或其他电极金属或Pt,Cr和Cu金属的组合以及扩散阻挡层组成。 另外的Ti层可以用于附着增强。 对于Cr层,第一金属层的厚度约为:200A; 铜层为0.5-10毫米; 1000 A-5000 A用于扩散阻挡层; 和Pt层的100A-2500A。
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公开(公告)号:US06339527B1
公开(公告)日:2002-01-15
申请号:US09470456
申请日:1999-12-22
IPC分类号: H01G4008
CPC分类号: H01L28/40 , H01L21/31683
摘要: The capacitor on a ceramic substrate one by unique film metallization including in one embodiment an in situ oxidation of titanium to create a metal oxide capacitor. The combination of metals when used with the appropriate optimized oxidation conditions and parameters ensures a high yielding capacitor with high capacitance in absence of noble metals and with ease of manufacture providing a low cost, high yield capacitor on ceramic.
摘要翻译: 陶瓷衬底上的电容器通过独特的膜金属化,包括在一个实施方案中,原位氧化钛以产生金属氧化物电容器。 当与适当的优化氧化条件和参数一起使用时,金属的组合确保了在不存在贵金属的情况下具有高电容的高产电容器,并且易于制造,在陶瓷上提供低成本,高产率的电容器。
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公开(公告)号:US06228682B1
公开(公告)日:2001-05-08
申请号:US09469157
申请日:1999-12-21
IPC分类号: H01L2144
CPC分类号: H01L24/11 , H01L25/165 , H01L2224/13099 , H01L2224/16227 , H01L2224/16265 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15159 , H01L2924/15312 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/30107 , H05K1/023 , H05K1/183 , H05K2201/1053 , H05K2201/10734 , H01L2924/00
摘要: The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.
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公开(公告)号:US06489686B2
公开(公告)日:2002-12-03
申请号:US09812091
申请日:2001-03-19
IPC分类号: H01L2348
CPC分类号: H01L24/11 , H01L25/165 , H01L2224/13099 , H01L2224/16227 , H01L2224/16265 , H01L2924/01033 , H01L2924/01082 , H01L2924/014 , H01L2924/09701 , H01L2924/12042 , H01L2924/14 , H01L2924/15159 , H01L2924/15312 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2924/19104 , H01L2924/30107 , H05K1/023 , H05K1/183 , H05K2201/1053 , H05K2201/10734 , H01L2924/00
摘要: The distance between a discrete or passive electrical component and an electrical semiconductor device and substrate or carrier is minimized by shortening the lead length connections of the passive component. One or more passive electronic components are mounted within the body of a carrier or board by creating a cavity in the substrate or carrier that is directly below a semiconductor device. The passive component is electrically connected to the substrate and device using solder bump technology resulting in much shorter lead length connections to and from the passive component.
摘要翻译: 离散或无源电气部件与电气半导体器件和衬底或载体之间的距离通过缩短被动部件的引线长度连接来最小化。 一个或多个无源电子部件通过在直接在半导体器件下面的衬底或载体中形成空腔而安装在载体或板的主体内。 无源部件使用焊料凸块技术电连接到基板和器件,导致与被动元件的连接更短的引线长度连接。
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7.
公开(公告)号:US5130067A
公开(公告)日:1992-07-14
申请号:US859093
申请日:1986-05-02
申请人: Philip L. Flaitz , Arlyne M. Flanagan , Joseph M. Harvilchuck , Lester W. Herron , John U. Knickerbocker , Robert W. Nufer , Charles H. Perry , Srinivasa N. Reddy , Steven P. Young
发明人: Philip L. Flaitz , Arlyne M. Flanagan , Joseph M. Harvilchuck , Lester W. Herron , John U. Knickerbocker , Robert W. Nufer , Charles H. Perry , Srinivasa N. Reddy , Steven P. Young
IPC分类号: C04B35/638 , C04B35/64 , H01L21/48
CPC分类号: C04B35/64 , C04B35/638 , H01L21/4807
摘要: A method for co-sintering ceramic/metal multi-layered ceramic substrates wherein X-Y shrinkage is controlled and X-Y distortion and Z-direction chamber are substantially eliminated. Binder-burnoff is substantially not aggravated during this process as well. The process is accomplished by applying selective forces to the surfaces of the ceramic substrates to control lateral movement while allowing Z direction shrinkage movement. Frictional force means, pneumatic forced means and weights are among the means used to supply forces. Cerium oxide is used in certain embodiments to enhance binder-burnoff.
摘要翻译: 一种陶瓷/金属多层陶瓷基板的共烧结方法,其中X-Y收缩被控制,并且基本上消除了X-Y变形和Z方向室。 在此过程中,粘结剂 - 烧毁也基本上不会加剧。 该过程通过向陶瓷基底的表面施加选择力来实现,以控制横向运动,同时允许Z方向收缩运动。 摩擦力意味着,气动强制手段和重量是用于供应力的手段之一。 在某些实施方案中使用氧化铈以增强粘合剂 - 燃烧。
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公开(公告)号:US5439636A
公开(公告)日:1995-08-08
申请号:US836675
申请日:1992-02-18
申请人: Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
发明人: Raschid J. Bezama , Jon A. Casey , Mario E. Ecker , Shaji Farooq , Irene S. Frantz , Katharine G. Frase , David H. Gabriels , Lester W. Herron , John U. Knickerbocker , Sara H. Knickerbocker , Govindarajan Natarajan , John Thomson , Yee-Ming Ting , Sharon L. Tracy , Robert M. Troncillito , Vivek M. Sura , Donald R. Wall , Giai V. Yen
IPC分类号: B28B11/02 , H01L21/48 , H01L21/768 , H01L23/15 , H01L23/522 , H05K1/03 , H05K1/14 , H05K3/46 , B22F3/00
CPC分类号: H05K1/142 , H01L21/4807 , H01L23/15 , H05K3/46 , H05K3/4629 , H01L2924/0002 , H01L2924/09701 , H05K1/0306 , H05K2201/09972 , Y10T428/12049 , Y10T428/12146 , Y10T428/16 , Y10T428/163 , Y10T428/166 , Y10T428/192
摘要: A large ceramic substrate article for electronic applications including at least one layer of sintered ceramic material, the layer including a plurality of greensheet segments of ceramic material joined edge to edge. Also disclosed is a method of fabricating a large ceramic greensheet article as well as a large ceramic substrate article.
摘要翻译: 一种用于电子应用的大型陶瓷衬底制品,包括至少一层烧结陶瓷材料,该层包括多个边缘到边缘连接的陶瓷材料毛坯块。 还公开了一种制造大型陶瓷毛坯制品的方法以及大型陶瓷基片制品。
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公开(公告)号:US06984792B2
公开(公告)日:2006-01-10
申请号:US10427459
申请日:2003-05-01
申请人: Peter J. Brofman , Shaji Farooq , John U. Knickerbocker , Scott I. Langenthal , Sudipta K. Ray , Kathleen A. Stalter
发明人: Peter J. Brofman , Shaji Farooq , John U. Knickerbocker , Scott I. Langenthal , Sudipta K. Ray , Kathleen A. Stalter
IPC分类号: H01R12/06
CPC分类号: H05K3/3436 , H01L23/49827 , H01L2224/05568 , H01L2224/05573 , H01L2224/16 , H01L2924/00014 , H01L2924/09701 , H05K2201/10378 , H05K2201/10424 , H05K2201/10674 , H05K2203/0415 , Y02P70/613 , Y10T29/49144 , Y10T29/49149 , H01L2224/05599
摘要: A pre-thermal reflown dielectric interposer having a plurality of vias traversing through the interposer which correspond to the I/O pads on a chip and substrate. Cone shaped solder elements reside within the vias, whereby these solder elements are cone shaped prior to thermal reflow to permit a reduced force for allowing some non-planarity for joining the chip to the substrate. The interposer may comprise a polyester film, glass, alumina, polyimide, a heat curable polymer or an inorganic powder filler in an organic material. The interposer may also have an adhesive or adhesive layers disposed on the linear surfaces thereof. The present pre-thermal reflown interposer prohibits contact between the solder joints by isolating each of the joints and corresponding bonding pads, as well as preventing over compression of the solder joints by acting as a stand off.
摘要翻译: 具有穿过插入件的多个通孔对应于芯片和基板上的I / O焊盘的预热退火介电插入器。 锥形焊料元件驻留在通孔内,由此这些焊料元件在热回流之前是锥形的,以允许减小的力以允许用于将芯片连接到衬底的一些非平面性。 中间层可以在有机材料中包含聚酯膜,玻璃,氧化铝,聚酰亚胺,热固化聚合物或无机粉末填料。 插入器也可以具有设置在其线性表面上的粘合剂或粘合剂层。 本发明的预热反射中介层通过隔离每个接头和相应的接合焊盘来防止焊点之间的接触,并且通过作为脱开来防止焊点过度压缩。
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10.
公开(公告)号:US06559527B2
公开(公告)日:2003-05-06
申请号:US09753819
申请日:2001-01-03
申请人: Peter Jeffrey Brofman , Shaji Farooq , John U. Knickerbocker , Scott Ira Langenthal , Sudipta Kumar Ray , Kathleen Ann Stalter
发明人: Peter Jeffrey Brofman , Shaji Farooq , John U. Knickerbocker , Scott Ira Langenthal , Sudipta Kumar Ray , Kathleen Ann Stalter
IPC分类号: H01L2302
CPC分类号: H01L24/81 , H01L24/11 , H01L24/13 , H01L2224/0401 , H01L2224/05666 , H01L2224/05671 , H01L2224/0603 , H01L2224/06505 , H01L2224/10135 , H01L2224/11002 , H01L2224/11472 , H01L2224/1184 , H01L2224/13017 , H01L2224/13019 , H01L2224/13082 , H01L2224/13111 , H01L2224/13116 , H01L2224/14 , H01L2224/1403 , H01L2224/14051 , H01L2224/141 , H01L2224/14505 , H01L2224/16058 , H01L2224/16238 , H01L2224/81136 , H01L2224/81139 , H01L2224/8121 , H01L2224/81815 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01013 , H01L2924/01022 , H01L2924/01024 , H01L2924/01027 , H01L2924/01029 , H01L2924/01033 , H01L2924/01042 , H01L2924/01049 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01082 , H01L2924/01322 , H01L2924/014 , H01L2924/10253 , H01L2924/14 , H01L2924/15787 , H01L2924/351 , H05K3/303 , H05K3/3436 , H05K3/3457 , H05K3/3473 , H05K2201/10992 , H05K2201/2036 , H05K2203/0113 , H05K2203/0465 , Y02P70/613 , H01L2924/00 , H01L2924/01083 , H01L2924/013 , H01L2924/00013 , H01L2924/00014
摘要: A method of forming non-spherically shaped solder interconnects, preferably conical, for attachment of electronic components in an electronic module. Preferably, the solder interconnects of the present invention are cone shaped and comprise of depositing a first solder followed by a second solder having a lower reflow temperature than the first solder. Warm placement of the electronic component at a somewhat elevated temperature than room temperature but less than the solder reflow temperature reduces the force required during placement of a semiconductor chip to a substrate. After warm placement, reflow of the module occurs at the lower reflow temperature of the second solder. The conical shape of the solder interconnects are formed by a heated coining die which may also coin a portion of the interconnects with flat surfaces for stand-offs. The ability of the cone shaped solder interconnects to meet the opposing surface of a chip or substrate at different heights accommodates the camber typically associated with chip and substrate surfaces.
摘要翻译: 形成用于将电子部件附接到电子模块中的非球形焊料互连(优选为圆锥形)的方法。 优选地,本发明的焊料互连件是锥形的,并且包括沉积第一焊料,接着是具有比第一焊料低的回流温度的第二焊料。 电子部件在比室温略高的温度但低于焊料回流温度的温度放置降低了将半导体芯片放置到衬底期间所需的力。 在温热放置之后,模块的回流在第二焊料的较低回流温度下发生。 焊接互连的圆锥形由加热的压印模具形成,其也可以将一部分互连件用平坦表面硬化以用于支架。 锥形焊料互连件在不同高度处与芯片或基板的相对表面相遇的能力适应通常与芯片和基板表面相关联的外倾。
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