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    Metal/dielectric laminate with electrodes and process thereof
    1.
    发明授权
    Metal/dielectric laminate with electrodes and process thereof 失效
    具有电极的金属/电介质层压板及其工艺

    公开(公告)号：US06509687B1

    公开(公告)日：2003-01-21

    申请号：US09450530

    申请日：1999-11-30

    申请人： Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

    发明人： Govindarajan Natarajan ,  Raschid J. Bezama ,  John U. Knickerbocker ,  Robert W. Pasco

    IPC分类号： H01J2964

    CPC分类号： H01J29/467 ,  H01J31/127

    摘要： The present invention relates generally to a new electrode forming metal/magnetic-ceramic laminate with through-holes and process thereof. More particularly, the invention encompasses a new process for fabrication of a large area ceramic laminate magnet with a significant number of holes, integrated metal plate(s) and co-sintered electrodes for electron and electron beam control. The present invention also relates to a magnetic matrix display (MMD), and electron beam source, and methods of manufacture thereof.

    摘要翻译： 本发明一般涉及具有通孔的新型电极形成金属/磁陶瓷层压体及其工艺。 更具体地，本发明包括用于制造具有大量孔的大面积陶瓷层压体磁体的新方法，用于电子和电子束控制的集成金属板和共烧结电极。 本发明还涉及磁矩阵显示器（MMD）和电子束源，及其制造方法。

    Low strain chip removal apparatus
    6.
    发明授权
    Low strain chip removal apparatus 有权
    低应变片去除装置

    公开(公告)号：US06745932B2

    公开(公告)日：2004-06-08

    申请号：US10235008

    申请日：2002-09-03

    申请人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    发明人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    IPC分类号： B23K1018

    CPC分类号： B23K1/018 ,  B23K2101/40

    摘要： A method and structure for a chip detach apparatus and method that limits the solder ball maximum shear rate and, more particularly, that delays the application of shear force until a minimum predefined temperature is reached. The chip detach apparatus and method can be applied to chips with high solder ball counts, chips with small solder ball sizes, and chips with weak surface strength. The chip detach apparatus and method measures and accounts for variability in the electronic module manufacturing and assembly.

    摘要翻译： 用于限制焊球最大剪切速率的切屑分离装置和方法的方法和结构，更具体地说，延迟剪切力的施加直到达到最小预定温度。 芯片分离装置和方法可以应用于具有高焊球计数的芯片，具有小焊球尺寸的芯片和具有弱表面强度的芯片。 芯片分离装置和方法测量并考虑了电子模块制造和组装中的变化。

    Method and apparatus to manufacture an electronic package with direct wiring pattern
    7.
    发明授权
    Method and apparatus to manufacture an electronic package with direct wiring pattern 失效
    制造具有直接布线图案的电子封装的方法和装置

    公开(公告)号：US06459039B1

    公开(公告)日：2002-10-01

    申请号：US09597906

    申请日：2000-06-19

    申请人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    发明人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    IPC分类号： H05K102

    CPC分类号： H01L23/49827 ,  H01L2224/16 ,  H01L2924/00014 ,  H01L2924/01079 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/3011 ,  H05K1/113 ,  H05K3/3436 ,  H05K2201/09836 ,  H05K2201/10378 ,  Y02P70/613 ,  H01L2224/0401

    摘要： An electronic package assembly for electrical interconnection between two electronic modules having differing conductive array parameters is disclosed. The electronic package assembly includes two electronic modules, providing between the two electronic modules an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer of the electronic package assembly, with the conductors including a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors of the interposer of the electronic package assembly. The first set of conductive arrays includes the same conductive array parameters as a first electronic module and the second set of conductive arrays includes the same conductive array parameters as a second electronic module.

    摘要翻译： 公开了一种用于具有不同导电阵列参数的两个电子模块之间的电互连的电子封装组件。 电子封装组件包括两个电子模块，在两个电子模块之间提供具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。 多个导体横穿电子封装组件的插入件的厚度，其中导体包括任选涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端 由此连接其中的第一和第二导电阵列的导体适于空间转换不同的参数以提供电互连。 导电矩阵围绕电子封装组件的插入件的导体。 第一组导电阵列包括与第一电子模块相同的导电阵列参数，第二组导电阵列包括与第二电子模块相同的导电阵列参数。

    Spatial transformation interposer for electronic packaging
    10.
    发明授权
    Spatial transformation interposer for electronic packaging 失效
    电子封装空间转换插件

    公开(公告)号：US06332782B1

    公开(公告)日：2001-12-25

    申请号：US09597919

    申请日：2000-06-19

    申请人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    发明人： Raschid J. Bezama ,  Govindarajan Natarajan ,  Robert W. Pasco

    IPC分类号： H01R1200

    CPC分类号： H05K1/141 ,  H01L2224/16225 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01R13/24 ,  H05K1/113 ,  H05K3/3436 ,  H05K3/368 ,  H05K7/1061 ,  H05K2201/049 ,  H05K2201/09836 ,  H05K2201/10378 ,  H05K2201/10734

    摘要： An interconnect substrate structure for electrical interconnection between two electronic modules having differing conductive array parameters. The interconnect structure comprises an interposer having a top surface and a bottom surface; a first set of conductive arrays having a first conductive array parameter on the top surface, and a second set of conductive arrays having a second conductive array parameter on the bottom surface, the second conductive array and the first conductive array having differing parameters. A plurality of conductors traverses a thickness of the interposer, with the conductors comprising a conductive material optionally coated with a dielectric material, the conductors having a first end at the first conductive arrays and a second end at the second conductive arrays, whereby the conductors connecting the first and second conductive arrays therein are adapted to spatially transform the differing parameters to provide an electrical interconnection. A conductive matrix surrounds the conductors. The first set of conductive arrays comprise the same conductive array parameters as a first electronic module and the second set of conductive arrays comprise the same conductive array parameters as a second electronic module.

    摘要翻译： 一种互连衬底结构，用于具有不同导电阵列参数的两个电子模块之间的电互连。 互连结构包括具有顶表面和底表面的插入件; 具有在顶表面上具有第一导电阵列参数的第一组导电阵列和在底表面上具有第二导电阵列参数的第二组导电阵列，所述第二导电阵列和第一导电阵列具有不同的参数。 多个导体横穿插入件的厚度，导体包括任选地涂覆有电介质材料的导电材料，导体在第一导电阵列处具有第一端，在第二导电阵列处具有第二端，由此导体连接 其中的第一和第二导电阵列适于空间转换不同的参数以提供电互连。 导电矩阵围绕导体。 第一组导电阵列包括与第一电子模块相同的导电阵列参数，并且第二组导电阵列包括与第二电子模块相同的导电阵列参数。