公开(公告)号：US20120167027A1

公开(公告)日：2012-06-28

申请号：US13172858

申请日：2011-06-30

申请人： YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： YA-LING HUANG ,  SHI-PIAO LUO ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： An electronic device and a method for checking layout distance of a printed circuit board (PCB) including presetting a checking condition to determine a reference layer. A high speed signal path is selected from a PCB design file, and a layer where the selected high speed signal path is located can be determined A reference layer of the determined layer is determined according to the checking condition, and a split line of the reference layer is determined. A shortest distance between each segment of the selected high speed signal path and the split line is calculated. If the shortest distance between a segment and the split line is less than the standard distance, layout of the segment is determined to be invalid.

摘要翻译： 一种用于检查印刷电路板（PCB）的布局距离的电子设备和方法，包括预设检查条件以确定参考层。 可以从PCB设计文件中选择高速信号路径，并且可以确定所选择的高速信号路径所在的层。根据检查条件确定确定层的参考层，并且确定参考的分割线 层被确定。 计算所选择的高速信号路径的每个段与分割线之间的最短距离。 如果段与分割线之间的最短距离小于标准距离，则段的布局被确定为无效。

公开(公告)号：US20120048610A1

公开(公告)日：2012-03-01

申请号：US12875156

申请日：2010-09-03

申请人： SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  SHEN-CHUN LI ,  CHIA-NAN PAI

发明人： SHOU-KUO HSU ,  YUNG-CHIEH CHEN ,  HSIEN-CHUAN LIANG ,  WEN-LAING TSENG ,  SHEN-CHUN LI ,  CHIA-NAN PAI

IPC分类号： H05K1/11

CPC分类号： H05K1/0251 ,  H05K1/115 ,  H05K2201/09836 ,  Y10T428/24917

摘要： A printed circuit board (PCB) includes two layers, two signal transmission traces, and a vertical interconnect access (via). The signal transmission traces are respectively arranged on the layers. The signal transmission traces are electrically connected to each other through the via. A centerline of the via with a vertical line of the layers form an acute angle θ, the angle θ is less than cos−1[(Lv2−Lt2)/(Lv2+Lt2)]. Wherein Lt is loss of the two signal transmitting traces in a unit length, and Lv is loss of the via in a unit length.

摘要翻译： 印刷电路板（PCB）包括两层，两条信号传输路径和一条垂直互连接口（via）。 信号传输迹线分别布置在层上。 信号传输迹线通过通孔彼此电连接。 具有垂直线的通孔的中心线形成锐角和角度;角度和角度; 小于cos-1 [（Lv2-Lt2）/（Lv2 + Lt2）]。 其中Lt是以单位长度丢失两个信号传输迹线，并且Lv是单位长度中的通孔的损失。

公开(公告)号：US20110094782A1

公开(公告)日：2011-04-28

申请号：US12647395

申请日：2009-12-25

申请人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/16

CPC分类号： H05K1/0253 ,  H05K1/181 ,  H05K2201/09381 ,  H05K2201/0969 ,  H05K2201/10015 ,  H05K2201/10022 ,  H05K2201/10636 ,  Y02P70/611

摘要： A printed circuit board includes a signal plane and a reference plane. The signal plane includes a pad, a passive element mounted on the pad, and a signal transmission line electrically connected to the passive element via the pad. The reference plane provides a return path for a signal transmitted through the passive element and the signal transmission line. A void is defined in the reference plane corresponding to the passive element, to increase a length of the return path. A length of a first axis, perpendicular to the signal transmission line, of the void satisfies a following equation: W 1 ≈ 8  Wpad + 10  T 0.8  Wtrace + T , wherein Wpad is a width of the pad, Wtrace is a width of the transmission line, T is the height of the pad.

摘要翻译： 印刷电路板包括信号平面和参考平面。 信号平面包括焊盘，安装在焊盘上的无源元件以及通过焊盘与无源元件电连接的信号传输线。 参考平面为通过无源元件和信号传输线传输的信号提供返回路径。 在对应于无源元件的参考平面中定义空隙，以增加返回路径的长度。 垂直于信号传输线的第一轴的长度满足以下等式：W 1≈8 Wpad + 10 T T W W W T T T + T，其中W pad是焊盘的宽度，Wtrace是 传输线的宽度，T是焊盘的高度。

公开(公告)号：US20130097576A1

公开(公告)日：2013-04-18

申请号：US13327771

申请日：2011-12-16

申请人： JIA-LU YE ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： JIA-LU YE ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： G06F17/50

CPC分类号： G06F17/5036

摘要： A computer-based method and a computing device for checking stub lengths of via stubs of a printed circuit board (PCB) layout are provided. The computing device displays a check interface, selects signal transmission line from a currently run PCB layout through the check interface, receives a reference stub length input through the check interface, and determines the actual stub length of each via stub of each via each selected signal transmission line connected to. The computing device further determines that a design of one via stub satisfies the design standards, if the actual stub length of the one stub via is less than or equal to the reference length, and determines that a design of one via stub does not satisfy the design standards if the actual stub length of the one via stub is greater than the reference stub length.

摘要翻译： 提供了一种基于计算机的方法和用于检查印刷电路板（PCB）布局的通孔短截线的短截线长度的计算装置。 计算装置显示检查接口，通过检查接口从当前运行的PCB布局中选择信号传输线，接收通过检查接口输入的参考短截线长度，并通过每个选定信号确定每个通孔短截线的实际短截线长度 传输线连接。 如果一个存根通孔的实际短截线长度小于或等于参考长度，则计算设备还确定一个通孔存根的设计满足设计标准，并且确定一个通孔存储体的设计不满足 如果一个通过存根的实际存根长度大于参考短截线长度，则设计标准。

公开(公告)号：US20130049461A1

公开(公告)日：2013-02-28

申请号：US13336000

申请日：2011-12-23

申请人： SHI-PIAO LUO ,  HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： SHI-PIAO LUO ,  HUA-LI ZHOU ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H02J4/00

CPC分类号： H05K1/0248 ,  H03K5/1534 ,  H03K19/00346 ,  H04L25/0278 ,  H05K1/0231 ,  H05K1/0246 ,  H05K2201/10015 ,  Y10T307/25

摘要： A circuit topology for multiple loads includes a driving terminal, first and second signal receiving terminals, and a capacitor. The driving terminal is connected to a node through a first transmission line. The node is connected to the first and second signal receiving terminals through second and third transmission lines. The second transmission line is longer than the third transmission line, and a difference between lengths of the second and third transmission lines is greater than a product of a transmission speed and a rise time of signals from the driving terminal. A first terminal of the capacitor is connected to the third transmission line. A second terminal of the capacitor is grounded. A distance between the capacitor and the second signal receiving terminal is less than a distance between the capacitor and the node.

摘要翻译： 用于多个负载的电路拓扑包括驱动端子，第一和第二信号接收端子以及电容器。 驱动终端通过第一传输线连接到节点。 节点通过第二和第三传输线连接到第一和第二信号接收终端。 第二传输线比第三传输线长，并且第二传输线和第三传输线的长度之间的差大于来自驱动终端的信号的传输速度和上升时间的乘积。 电容器的第一端子连接到第三传输线。 电容器的第二个端子接地。 电容器和第二信号接收端子之间的距离小于电容器和节点之间的距离。

公开(公告)号：US20120243193A1

公开(公告)日：2012-09-27

申请号：US13491526

申请日：2012-06-07

申请人： CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/18

CPC分类号： H05K1/0295 ,  H05K1/0239 ,  H05K1/0245 ,  H05K1/113 ,  H05K3/429 ,  H05K2201/044 ,  H05K2201/09254 ,  H05K2201/10015 ,  H05K2201/10545 ,  H05K2201/10636 ,  Y02P70/611

摘要： A motherboard interconnection method includes positioning a first and a third electronic elements on a top layer of a motherboard interconnection device, and positioning a second and a fourth electronic elements on a bottom layer of the motherboard interconnection device. The method connects a first end of the first electronic element on the top layer to the first end of the second electronic element on the bottom layer with a first via hole, and connects the first end of the third electronic element on the top layer to the first end of the fourth electronic element on the bottom layer with a second via hole. The method further connects a second ends of the two electronic elements on the top layer to a first part, and connects the second ends of the two electronic elements on the bottom layer to a second part.

摘要翻译： 母板互连方法包括将第一和第三电子元件定位在母板互连装置的顶层上，并将第二和第四电子元件定位在母板互连装置的底层上。 该方法通过第一通孔将顶层上的第一电子元件的第一端与底层上的第二电子元件的第一端连接，并将顶层上的第三电子元件的第一端连接到 第四电子元件的第一端部具有第二通孔。 该方法还将顶层上的两个电子元件的第二端连接到第一部分，并且将底层上的两个电子元件的第二端连接到第二部分。

公开(公告)号：US20120007688A1

公开(公告)日：2012-01-12

申请号：US12960321

申请日：2010-12-03

申请人： HUA-LI ZHOU ,  MING WEI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： HUA-LI ZHOU ,  MING WEI ,  CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H01P3/08

CPC分类号： H05K1/0245 ,  H05K2201/09727

摘要： A printed circuit board includes an insulation layer and a signal layer attached to the insulation layer. The signal layer includes a pair of differential transmission lines. Width W of each of the differential transmission lines is changed according to change of space S between the differential transmission lines, based on the following formula: W = C   1 × H × ( C   2 × H 0.8  W 0 + T ) C   3 ×  C   4 × S 0 H - 1 1 - C   3 ×  C   4 × S H - 1.25  T In above formula, C1=7.475, C2=5.98, C3=0.48, C4=−0.96, H is a thickness of the insulation layer, W0 is an original width of each of the differential transmission lines, and S0 is an original space between the differential transmission lines, and T is a thickness of each of the differential transmission lines.

摘要翻译： 印刷电路板包括绝缘层和附着到绝缘层的信号层。 信号层包括一对差动传输线。 差分传输线的宽度W根据以下公式根据差分传输线之间的空间S的变化而改变：W = C 1 / H×（C 2 2×H 0.8 W 0 + 在上式中，C 1 = 7.475，C 2 = 5.98，C 3 = C 9，C 3 = 0.48，C4 = -0.96，H是绝缘层的厚度，W0是差分传输线的原始宽度，S0是差动传输线之间的原始空间，T是各个差分传输线的厚度 差动传输线。

公开(公告)号：US20100276192A1

公开(公告)日：2010-11-04

申请号：US12503684

申请日：2009-07-15

申请人： CHIA-NAN PAI ,  SHOU-KUO HSU

发明人： CHIA-NAN PAI ,  SHOU-KUO HSU

IPC分类号： H05K1/11 ,  H05K3/42

CPC分类号： H05K1/115 ,  H05K1/0251 ,  H05K3/429 ,  H05K3/4623 ,  H05K2201/09309 ,  H05K2201/096 ,  H05K2203/063 ,  Y10T29/49165

摘要： A method for removing a stub of a via hole includes copperizing a wall of a via hole in a top layer of a printed circuit board (PCB) if signal lines are located on the top layer of the PCB, and a wall of the via hole in a bottom layer of the PCB is not copperized. The method further includes connecting the top layer and the bottom layer of the PCB using a connection layer.

摘要翻译： 用于去除通孔的短截线的方法包括如果信号线位于PCB的顶层上，则在印刷电路板（PCB）的顶层中的通孔的壁上铜化，并且通孔的壁 在PCB的底层没有铜化。 该方法还包括使用连接层连接PCB的顶层和底层。

公开(公告)号：US20100258337A1

公开(公告)日：2010-10-14

申请号：US12430133

申请日：2009-04-27

申请人： SHOU-KUO HSU ,  CHIA-NAN PAI

发明人： SHOU-KUO HSU ,  CHIA-NAN PAI

IPC分类号： H05K1/00

CPC分类号： H05K1/0245 ,  H05K1/0253 ,  H05K1/0393 ,  H05K2201/0715 ,  H05K2201/09236 ,  H05K2201/09672 ,  H05K2201/0969

摘要： A flexible printed circuit board (FPCB) includes a signal layer, upper and lower ground layers, and two dielectric layers. The signal layer includes a differential pair comprising two transmission lines to transmit a pair of differential signals. The dielectric layers are located on and under the signal layer to sandwich the signal layer. The upper ground layer is attached to the dielectric layer on the signal layer, opposite to the signal layer. The lower ground layer is attached to the dielectric layer under the signal layer, opposite to the signal layer. Each ground layer includes a grounded sheet made of conductive material. Two voids are defined in each ground layer and located at opposite sides of the corresponding grounded sheet. Distances between the middle line of the grounded sheet of each ground layer and middle lines of the two transmission lines are equal.

摘要翻译： 柔性印刷电路板（FPCB）包括信号层，上下接地层和两个电介质层。 信号层包括差分对，该差分对包括用于发送一对差分信号的两条传输线。 电介质层位于信号层之上和之下，以夹住信号层。 上层接地层与信号层的电介质层相连，与信号层相反。 下部接地层附着在与信号层相反的信号层下面的电介质层上。 每个接地层包括由导电材料制成的接地片。 在每个接地层中定义两个空隙，并且位于相应接地片的相对侧。 每个接地层的接地片的中间线与两条传输线的中间线之间的距离相等。

公开(公告)号：US20120331437A1

公开(公告)日：2012-12-27

申请号：US13407768

申请日：2012-02-29

申请人： CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

发明人： CHIA-NAN PAI ,  SHOU-KUO HSU ,  YA-LING HUANG

IPC分类号： G06F17/50

CPC分类号： G06F17/5081

摘要： In a method for checking layout of a printed circuit board (PCB) using an electronic device, a signal line is selected from a layout diagram of the PCB. The method searches for signal lines which have an acute angle when deviating from a straight line in the layout diagram of the PCB. The method further locates attribute data of the searched signal lines in the layout diagram of the PCB, and displays the attribute data of the searched signal lines on a display device of the electronic device.

摘要翻译： 在使用电子设备检查印刷电路板（PCB）的布局的方法中，从PCB的布局图中选择信号线。 该方法搜索在PCB布局图中偏离直线时具有锐角的信号线。 该方法进一步在PCB的布局图中定位搜索到的信号线的属性数据，并将所搜索的信号线的属性数据显示在电子设备的显示装置上。