公开(公告)号：US20100032198A1

公开(公告)日：2010-02-11

申请号：US12528401

申请日：2008-02-20

Applicant: Hirobumi Inoue

Inventor： Hirobumi Inoue

IPC: H05K1/02

CPC classification number: H05K1/025 ,  H05K1/0218 ,  H05K1/024 ,  H05K1/183 ,  H05K3/403 ,  H05K2201/0715 ,  H05K2201/091 ,  H05K2201/09154 ,  H05K2201/09827 ,  H05K2201/10446 ,  H05K2201/10484

Abstract: An inclined peripheral portion 103 having a tapered shape in a cross-sectional view, in which the thickness thereof is reduced toward the edge of an interconnection substrate 102, is provided at the edge of the interconnection substrate 102. In addition, inner layers 112 are provided such that the distance therebetween is reduced toward the edge of the interconnection substrate in the inclined peripheral portion 103. A first interconnection conductor 104 and a second interconnection conductor 105 are provided on both inclined planes of the inclined peripheral portion 103 so as to be electrically connected to each other at the leading end of the inclined peripheral portion 103.

Abstract translation: 在互连基板102的边缘处设置有在横截面视图中具有锥形形状的倾斜周边部分103，其中其厚度朝向互连基板102的边缘减小。另外，内层112 被设置为使得它们之间的距离朝向倾斜周边部分103中的互连基板的边缘减小。第一互连导体104和第二互连导体105设置在倾斜周边部分103的两个倾斜平面上，以便电 在倾斜周边部103的前端彼此连接。

公开(公告)号：US07594644B2

公开(公告)日：2009-09-29

申请号：US11267328

申请日：2005-11-07

Applicant: Takao Yamazaki ,  Hirobumi Inoue ,  Ichiro Hazeyama ,  Sakae Kitajo ,  Masahiro Kubo ,  Yoshimichi Sogawa ,  Hidehiko Kuroda

Inventor： Takao Yamazaki ,  Hirobumi Inoue ,  Ichiro Hazeyama ,  Sakae Kitajo ,  Masahiro Kubo ,  Yoshimichi Sogawa ,  Hidehiko Kuroda

IPC: B25B11/00

CPC classification number: H01L25/50 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.

Abstract translation: 提供一种半导体器件，包括具有电路和电路的至少一个电极的半导体元件，具有至少一个电极焊盘并围绕半导体元件的柔性基板，用于将电极与电极焊盘连接的导体，以及多个 在电极焊盘上的焊料凸点，其中面对半导体元件的焊料凸块的表面和柔性基板之间的至少第一部分不通过粘附固定。

公开(公告)号：US07321166B2

公开(公告)日：2008-01-22

申请号：US11274182

申请日：2005-11-16

Applicant: Jun Sakai ,  Hirobumi Inoue ,  Kazuhiro Motonaga

Inventor： Jun Sakai ,  Hirobumi Inoue ,  Kazuhiro Motonaga

IPC: H01L23/12

CPC classification number: H05K1/0218 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/50 ,  H01L2224/16225 ,  H01L2224/16235 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01057 ,  H01L2924/01078 ,  H01L2924/09701 ,  H01L2924/15173 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/19105 ,  H01L2924/3011 ,  H01L2924/3025 ,  H05K1/0219 ,  H05K1/0231 ,  H05K1/0298 ,  H05K1/112 ,  H05K2201/0715 ,  H01L2224/0401

Abstract: It is to provide a wiring board for a semiconductor integrated circuit package, which exhibits an excellent signal property and a high effect for decreasing the switching noise at the time of mounting an LSI of an area-array structure. In a multilayer wiring board for a package, which comprises, on a wiring layer of an LSI chip mount surface, a ground pad, a power supply pad, and a signal pad for mounting LSI chip, and a ground plane that extends around a group of those pads, the ground pad disposed on the inner side, among the above-described pads, is connected to the ground plane that surrounds the pad group through a connecting wiring.

Abstract translation: 提供一种用于半导体集成电路封装的布线板，其具有优异的信号特性和用于降低安装区域阵列结构的LSI时的开关噪声的高效果。 在一种用于封装的多层布线板中，其包括在LSI芯片安装表面的布线层上的接地焊盘，电源焊盘和用于安装LSI芯片的信号焊盘以及围绕一组延伸的接地平面 在这些焊盘中，设置在上述焊盘中的内侧的接地焊盘通过连接布线连接到围绕焊盘组的接地平面。

公开(公告)号：US20070033564A1

公开(公告)日：2007-02-08

申请号：US11473345

申请日：2006-06-23

Applicant: Hirobumi Inoue ,  Daisuke Ohshima ,  Jun Sakai ,  Mitsuru Furuya

Inventor： Hirobumi Inoue ,  Daisuke Ohshima ,  Jun Sakai ,  Mitsuru Furuya

IPC: G06F17/50

CPC classification number: G06F17/5036 ,  G06F2217/40

Abstract: An analysis method of designing transmission lines of an integrated circuit packaging board including an integrated circuit chip, a printed circuit board, and an interposer disposed between the integrated circuit chip and the printed circuit board. A reference data file having information for dividing a series of transmission lines into connecting sections and/or continuous sections and a division model file having information on analysis models of a connecting section and a continuous section is prepared. The connecting sections are extracted from the series of transmission lines with reference to connection information. Boundaries for dividing the series of transmission lines into sections is determined with reference to the reference data file to generate division models. The division models are synthesized to form a synthesized model of the series of transmission lines to analyze electrical characteristics of the series of transmission lines.

Abstract translation: 包括设置在集成电路芯片和印刷电路板之间的集成电路芯片，印刷电路板和插入器的集成电路封装板的传输线的分析方法。 准备具有用于将一系列传输线分成连接部分和/或连续部分的信息的参考数据文件和具有关于连接部分和连续部分的分析模型的信息的分割模型文件。 参考连接信息，从一系列传输线中提取连接部分。 参考参考数据文件确定将一系列传输线划分为多个部分的边界，以生成分割模型。 合成分割模型以形成一系列传输线的合成模型，以分析一系列传输线的电气特性。

公开(公告)号：US20060055053A1

公开(公告)日：2006-03-16

申请号：US11267328

申请日：2005-11-07

Applicant: Takao Yamazaki ,  Hirobumi Inoue ,  Ichiro Hazeyama ,  Sakae Kitajo ,  Masahiro Kubo ,  Yoshimichi Sogawa ,  Hidehiko Kuroda

Inventor： Takao Yamazaki ,  Hirobumi Inoue ,  Ichiro Hazeyama ,  Sakae Kitajo ,  Masahiro Kubo ,  Yoshimichi Sogawa ,  Hidehiko Kuroda

IPC: H01L23/48

CPC classification number: H01L25/50 ,  H01L23/4985 ,  H01L25/105 ,  H01L2224/02371 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05571 ,  H01L2224/16225 ,  H01L2224/32014 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058 ,  H01L2924/00014 ,  H01L2924/09701 ,  H01L2924/15311 ,  H01L2924/3511 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A semiconductor device is provided including a semiconductor element having a circuit and at least one electrode of the circuit, a flexible substrate having at least one electrode pad and surrounding the semiconductor element, a conductor for connecting the electrode with the electrode pad, and a plurality of solder bumps on the electrode pad, wherein at least a first portion between a surface facing the solder bumps of the semiconductor element and the flexible substrate is not fixed by adhesion.

公开(公告)号：US06433410B1

公开(公告)日：2002-08-13

申请号：US09821690

申请日：2001-03-30

Applicant: Michinobu Tanioka ,  Takahiro Kimura ,  Hirobumi Inoue ,  Hiroo Ito ,  Yoshihito Fukasawa

Inventor： Michinobu Tanioka ,  Takahiro Kimura ,  Hirobumi Inoue ,  Hiroo Ito ,  Yoshihito Fukasawa

IPC: H01L23495

Abstract: There is provided a semiconductor device tester including (a) a tester substrate having the same structure as a structure of a substrate as a product except that a semiconductor device is not mounted on the tester substrate, (b) an electrically conductive sheet covering therewith a first area in which the semiconductor device is to be mounted on the tester substrate, the electrically conductive sheet being electrically insulating in a certain direction, and (c) a holder supporting a semiconductor device to be tested therewith, and compressing the semiconductor device onto the electrically conductive sheet to thereby electrically connect an externally projecting terminal of the semiconductor device to a connection terminal mounted on the tester substrate in the first area.

公开(公告)号：US06310483B1

公开(公告)日：2001-10-30

申请号：US09183883

申请日：1998-10-30

Applicant: Toru Taura ,  Hirobumi Inoue ,  Masao Tanehashi ,  Kouji Matsunaga ,  Yuuichi Yamagishi ,  Satoshi Hayakawa ,  Hironori Tsugane

Inventor： Toru Taura ,  Hirobumi Inoue ,  Masao Tanehashi ,  Kouji Matsunaga ,  Yuuichi Yamagishi ,  Satoshi Hayakawa ,  Hironori Tsugane

IPC: G01R3102

CPC classification number: G01R1/06772

Abstract: A high-frequency probe according to the present invention comprises a probe chip that has an end part that is pressed to an electrode and is covered by a electrically conductive outer enclosure, and slides in a vertical direction by an inner surface of this electrically conductive outer enclosure inside this electrically conductive outer enclosure. A signal conductive pattern is fixed inside this probe chip and is connected with a inner conductor having elasticity. The inner conductor can be bent in the vertical direction at a central part of a hole having an opening, which is sufficiently long in the vertical direction, in the center space of a ground conductor, which is fixed to an end part of the main block, when the inner conductor is pressed due to contact of the end part. In addition, the high-frequency probe has a thin shape of a maximum thickness in a transverse direction which is perpendicular to the vertical direction that is a direction of the probe being pressed to a device electrode. The maximum thickness is substantially equal to a pitch between device electrodes, and can be formed in the construction of unifying a plurality of high-frequency probes.

Abstract translation: 根据本发明的高频探针包括探针芯片，其具有被压到电极并被导电外壳覆盖的端部，并且通过该导电外壳的内表面在垂直方向上滑动 封装在该导电外壳内。 信号导电图案固定在该探针芯片内，并与具有弹性的内部导体连接。 内导体可以在具有开口的中心部分的垂直方向上弯曲，该中心部分在接地导体的中心空间中在垂直方向上足够长，该接地导体的中心空间固定到主块的端部 当内导体由于端部的接触被按压时。 此外，高频探头具有垂直于被探针被压向器件电极的方向的垂直方向的横向上的最大厚度的薄形状。 最大厚度基本上等于器件电极之间的间距，并且可以在统一多个高频探针的结构中形成。

公开(公告)号：US06281691B1

公开(公告)日：2001-08-28

申请号：US09328362

申请日：1999-06-09

Applicant: Kouji Matsunaga ,  Hirobumi Inoue ,  Masao Tanehashi ,  Toru Taura ,  Masahiko Nikaidou ,  Yuuichi Yamagishi ,  Satoshi Hayakawa

Inventor： Kouji Matsunaga ,  Hirobumi Inoue ,  Masao Tanehashi ,  Toru Taura ,  Masahiko Nikaidou ,  Yuuichi Yamagishi ,  Satoshi Hayakawa

IPC: G01R3102

CPC classification number: G01R1/06738 ,  G01R1/06772 ,  Y10T29/49123

Abstract: In a tip portion structure basically having a substrate, a plate spring, and a ground block, the substrate is attached to a signal line on a back surface of the substrate and is contacted on the tip with the signal electrode of the DUT placed on a device stage. The plate spring is made of a resilient material, placed on the front side of the substrate, and positioned to apply a pressure to the substrate. The ground block is positioned between the signal line and the device stage functioned as a ground electrode of the DUT. Alternatively, the tip portion structure further may have a ground plate or a ground surface formed of a conductive thin plate covering entirely the front surface of the substrate, and shaped to surround the signal line in cooperation with the ground block . A plurality of the signal lines may be arranged in parallel on the same plane of the substrate. Another tip portion structure is based on a coaxial cable to be cut from the center at a plane perpendicular to the axial direction thereof along one or more oblique plane. A metal ring fitted over a periphery of the coaxial outer conductor may be used.

Abstract translation: 在基本上具有基板，板簧和接地块的尖端部分结构中，将基板附着到基板的背面上的信号线上，并将其与被放置在基板上的DUT的信号电极接触 设备阶段 板簧由弹性材料制成，放置在基片的正面，并定位成对基片施加压力。 接地块位于作为DUT接地电极的信号线和器件级之间。 或者，尖端部分结构还可以具有由完全覆盖基板的前表面的导电薄板形成的接地板或接地表面，并且成形为与接地块一起包围信号线。 多个信号线可以平行布置在基板的同一平面上。 另一个尖端部分结构是基于同轴电缆，沿着一个或多个倾斜平面在垂直于其轴向方向的平面处从中心切割。 可以使用安装在同轴外导体周边上的金属环。