公开(公告)号：US10347536B2

公开(公告)日：2019-07-09

申请号：US16203605

申请日：2018-11-28

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L21/8238 ,  H01L27/06 ,  H01L27/092 ,  H01L23/535 ,  H01L21/84 ,  H01L27/088 ,  H01L27/12 ,  H01L27/02

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US10236183B2

公开(公告)日：2019-03-19

申请号：US15652786

申请日：2017-07-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert ,  Rita Rooyackers

IPC: H01L29/778 ,  H01L21/762 ,  H01L21/18 ,  H01L21/02 ,  H01L21/768 ,  H01L23/535 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L29/04 ,  H01L21/84 ,  H01L29/78 ,  H01L23/66

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

公开(公告)号：US20180025911A1

公开(公告)日：2018-01-25

申请号：US15652786

申请日：2017-07-18

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert ,  Rita Rooyackers

IPC: H01L21/18 ,  H01L23/00 ,  H01L21/02 ,  H01L25/00 ,  H01L23/535 ,  H01L21/768 ,  H01L29/04 ,  H01L25/065

CPC classification number: H01L21/187 ,  H01L21/02387 ,  H01L21/76251 ,  H01L21/76895 ,  H01L21/845 ,  H01L23/535 ,  H01L23/66 ,  H01L24/32 ,  H01L25/0655 ,  H01L25/50 ,  H01L29/04 ,  H01L29/20 ,  H01L29/365 ,  H01L29/66462 ,  H01L29/7781 ,  H01L29/7787 ,  H01L29/7851 ,  H01L2224/32501

Abstract: A method for forming a semiconductor structure by bonding a donor substrate to a carrier substrate is disclosed herein. The donor substrate may include a plurality of semiconductor layers epitaxially grown on top of one another in, and optionally above, a trench of the donor substrate. The carrier substrate may include a first semiconductor device thereon. The method may include removing at least part of the donor substrate in such a way as to expose a semiconductor layer grown on the bottom of the trench, removing at least part of the exposed semiconductor layer, thereby modifying the plurality of semiconductor layers, and forming a second semiconductor device from the modified plurality of semiconductor layers.

公开(公告)号：US20150279947A1

公开(公告)日：2015-10-01

申请号：US14671134

申请日：2015-03-27

Applicant: IMEC VZW

Inventor： Niamh Waldron ,  Clement Merckling ,  Nadine Collaert

IPC: H01L29/41 ,  H01L29/423 ,  H01L29/78 ,  H01L29/20 ,  H01L29/66 ,  H01L29/04

CPC classification number: H01L27/0886 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/02381 ,  H01L21/02538 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02639 ,  H01L29/04 ,  H01L29/0649 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/1079 ,  H01L29/20 ,  H01L29/401 ,  H01L29/413 ,  H01L29/42392 ,  H01L29/66469 ,  H01L29/66545 ,  H01L29/6681 ,  H01L29/775 ,  H01L29/7853 ,  H01L29/78681 ,  H01L29/78696

Abstract: The disclosed technology generally relates to semiconductor devices and more particularly to a gate-all-around semiconductor device, and methods of fabricating the same. In one aspect, the method comprises providing on a semiconductor substrate between STI regions at least one suspended nanostructure anchored by a source region and a drain region. The suspended nanostructure is formed of a crystalline semiconductor material that is different from a crystalline semiconductor material of the semiconductor substrate. A gate stack surrounds the at least one suspended nanostructure.

Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及栅极全能半导体器件及其制造方法。 一方面，该方法包括在STI区域之间的半导体衬底上提供由源区域和漏极区域锚定的至少一个悬浮纳米结构。 悬浮的纳米结构由与半导体衬底的结晶半导体材料不同的结晶半导体材料形成。 一个栅极叠层围绕至少一个悬浮的纳米结构。

公开(公告)号：US20230010039A1

公开(公告)日：2023-01-12

申请号：US17859294

申请日：2022-07-07

Applicant: IMEC VZW ,  Katholieke Universiteit Leuven, KU LEUVEN R&D

Inventor： Martin Heilmann ,  Ming Zhao ,  Nadine Collaert ,  Bertrand Parvais ,  Sachin Yadav

IPC: H01L21/8258 ,  H01L27/06 ,  H01L21/02 ,  C30B29/06 ,  C30B25/18 ,  C30B29/40 ,  C23C16/30 ,  C23C16/02

Abstract: A method for manufacturing a semiconductor structure is provided. The method includes a III-V semiconductor device in a first region of a base substrate and a further device in a second region of the base substrate. The method includes: (a) obtaining a base substrate comprising the first region and the second region, different from the first region; (b) providing a buffer layer over a surface of the base substrate at least in the first region, wherein the buffer layer comprises at least one monolayer of a first two-dimensional layered crystal material; (c) forming, over the buffer layer in the first region, and not in the second region, a III-V semiconductor material; and (d) forming, in the second region, at least part of the further device. A semiconductor structure is also provided.

公开(公告)号：US20190096764A1

公开(公告)日：2019-03-28

申请号：US16203605

申请日：2018-11-28

Applicant: IMEC VZW

Inventor： Amey Mahadev Walke ,  Nadine Collaert

IPC: H01L21/822 ,  H01L23/535 ,  H01L21/84 ,  H01L27/06 ,  H01L21/8238 ,  H01L27/092

CPC classification number: H01L21/8221 ,  H01L21/823871 ,  H01L21/84 ,  H01L23/535 ,  H01L27/0207 ,  H01L27/0694 ,  H01L27/088 ,  H01L27/092 ,  H01L27/1203

Abstract: Disclosed herein is a semiconductor structure including: a host substrate and one or more bonding layers on top of the host substrate. The structure further includes an entity on the one or more bonding layers, where the entity includes two transistors on opposite sides of a common layer of channel material, where each transistor includes a gate, where both gates overlap each other, where both transistors share the same source and drain regions, and where each transistor have a channel defined within a same portion of the common layer of channel material overlapped by both transistor gates.

公开(公告)号：US09633891B2

公开(公告)日：2017-04-25

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/32 ,  H01L21/3205 ,  H01L29/06 ,  H01L29/423 ,  H01L29/66 ,  H01L29/786

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

公开(公告)号：US20160141391A1

公开(公告)日：2016-05-19

申请号：US14938169

申请日：2015-11-11

Applicant: IMEC VZW

Inventor： Clement Merckling ,  Nadine Collaert

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78 ,  H01L29/20

CPC classification number: H01L29/66795 ,  H01L21/02381 ,  H01L21/02387 ,  H01L21/02392 ,  H01L21/02395 ,  H01L21/0243 ,  H01L21/02455 ,  H01L21/02513 ,  H01L21/02546 ,  H01L21/02549 ,  H01L21/0262 ,  H01L21/02639 ,  H01L21/02658 ,  H01L21/02661 ,  H01L21/76224 ,  H01L29/20 ,  H01L29/41725 ,  H01L29/7848

Abstract: A method for growing a III-V semiconductor structure on a SinGe1-n substrate, wherein n is from 0 to 1 is provided. The method includes the steps of: (a) bringing a SinGe1-n substrate to a high temperature; (b) exposing the area to a group V precursor in a carrier gas for from 5 to 30 min, thereby forming a doped region at said area; (c) bringing the SinGe1-n substrate to a low temperature; (d) exposing the doped region to a group III precursor in a carrier gas and to a group V precursor in a carrier gas until a nucleation layer of III-V material of from 5 to 15 nm is formed on the nucleation layer; (e) bringing the SinGe1-n substrate to an intermediate temperature; and (f) exposing the nucleation layer to a group III precursor in a carrier gas and to a group V precursor in a carrier gas.

Abstract translation: 提供了一种在SinGe1-n衬底上生长III-V半导体结构的方法，其中n为0至1。 该方法包括以下步骤：（a）使SinGe1-n衬底达到高温; （b）将载体气体中的V族前体暴露于5〜30分钟，由此在该区域形成掺杂区域; （c）使SinGe1-n基板处于低温; （d）将载体气体中的掺杂区域暴露于III族前体，并在载气中暴露于V族前体，直至在成核层上形成5〜15nm的III-V材料的成核层; （e）使SinGe1-n基板达到中间温度; 和（f）将成核层暴露于载气中的III族前体和载气中的V族前体。

公开(公告)号：US20160126131A1

公开(公告)日：2016-05-05

申请号：US14924832

申请日：2015-10-28

Applicant: IMEC VZW

Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

公开(公告)号：US11322390B2

公开(公告)日：2022-05-03

申请号：US16844845

申请日：2020-04-09

Applicant: IMEC vzw

Inventor： Amey Mahadev Walke ,  Niamh Waldron ,  Nadine Collaert ,  Ming Zhao

IPC: H01L25/16 ,  H01L21/762 ,  H01L29/66 ,  H01L29/778 ,  H01L29/20 ,  H01L29/205 ,  H01L29/423

Abstract: The disclosed technology relates generally to the field of semiconductor devices, and more particularly to co-integration of GaN-based devices with Si-based devices. In one aspect, a method of forming a semiconductor device includes forming a first wafer including, on a front side thereof, a III-V semiconductor layer stack formed on a first substrate and a first bonding layer. The III-V semiconductor layer stack includes a GaN-based device layer structure formed on the first substrate. The method additionally includes, subsequent to forming the first wafer, bonding the first bonding layer to a second bonding layer of a second wafer. The second wafer includes a second silicon substrate supporting an active device layer, a back-end-of-line interconnect structure and the second bonding layer. The method further comprises, subsequent to bonding, thinning the first wafer from a backside, wherein thinning includes removing at least the first substrate. In another aspect, a semiconductor device includes a cointegrated N-polar HEMT.