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    SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME
    13.
    发明申请
    SEMICONDUCTOR DEVICES COMPRISING MULTIPLE CHANNELS AND METHOD OF MAKING SAME 有权
    包含多个通道的半导体器件及其制造方法

    公开(公告)号：US20170025314A1

    公开(公告)日：2017-01-26

    申请号：US15199535

    申请日：2016-06-30

    Applicant: IMEC VZW

    Inventor： Liesbeth Witters ,  Kurt Wostyn

    IPC: H01L21/8238 ,  H01L21/3065 ,  H01L29/06 ,  H01L29/78 ,  H01L29/66 ,  H01L27/092 ,  H01L29/423

    CPC classification number: H01L21/823807 ,  B82Y10/00 ,  B82Y40/00 ,  H01L21/3065 ,  H01L21/823412 ,  H01L27/092 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/42356 ,  H01L29/42392 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827 ,  H01L29/7849 ,  H01L29/78696

    Abstract: The disclosed technology generally relates to semiconductor devices, and more particularly to transistor devices comprising multiple channels. In one aspect, a method of fabricating a transistor device comprises forming on the substrate a plurality of vertically repeating layer stacks each comprising a first layer, a second layer and a third layer stacked in a predetermined order, wherein each of the first, second and third layers is formed of silicon, silicon germanium or germanium and has a different germanium concentration compared to the other two of the first, second and third layers. The method additionally includes selectively removing the first layer with respect to the second and third layers from each of the layer stacks, such that a gap interposed between the second layer and the third layer is formed in each of the layer stacks. The method further includes selectively removing the second layer from each of the layer stacks with respect to the third layer, wherein removing the second layer comprises at least partially removing the second layer through the gap, thereby defining the channels comprising a plurality of vertically arranged third layers.

    Abstract translation: 所公开的技术通常涉及半导体器件，更具体地涉及包括多个通道的晶体管器件。 一方面，一种制造晶体管器件的方法包括在衬底上形成多个垂直重复的层堆叠，每个堆叠层包括以预定顺序堆叠的第一层，第二层和第三层，其中第一，第二和第 第三层由硅，硅锗或锗形成，并且与第一层，第二层和第三层中的其它两层相比具有不同的锗浓度。 该方法还包括相对于每个层堆叠的第二层和第三层选择性地去除第一层，使得在每个层堆叠中形成插入在第二层和第三层之间的间隙。 所述方法还包括相对于所述第三层从所述层堆叠中选择性地去除所述第二层，其中，去除所述第二层包括通过所述间隙至少部分地移除所述第二层，从而限定所述通道，所述通道包括多个垂直布置的第三层 层。

    Contact formation in Ge-containing semiconductor devices
    14.
    发明授权
    Contact formation in Ge-containing semiconductor devices 有权
    含Ge半导体器件中的接触层形成

    公开(公告)号：US09343329B2

    公开(公告)日：2016-05-17

    申请号：US14620766

    申请日：2015-02-12

    Applicant: IMEC VZW

    Inventor： Alexey Milenin ,  Liesbeth Witters

    IPC: H01L21/3205 ,  H01L21/311 ,  H01L29/16 ,  H01L29/78 ,  H01L29/66 ,  H01L21/285 ,  H01L29/417 ,  H01L29/45

    CPC classification number: H01L21/32051 ,  H01L21/28568 ,  H01L21/31116 ,  H01L21/31144 ,  H01L29/16 ,  H01L29/41791 ,  H01L29/45 ,  H01L29/66795 ,  H01L29/7842 ,  H01L29/7851

    Abstract: A process for creating a contact on a Ge-containing contact region of a semiconductor structure, said process comprising the steps of: providing said semiconductor structure comprising: (i) a Ge-containing contact region, (ii) optionally, a SiO2 layer coating said Ge-containing contact region, (iii) a Si3N4 layer coating said SiO2 layer if present or said Ge-containing contact region; etching selectively the Si3N4 layer by means of an inductively coupled plasma, thereby exposing the underlying SiO2 layer if present or the Ge-containing contact region; etching selectively the SiO2 layer if present, thereby exposing the SiGe:B contact region; and creating said contact on said Ge-containing contact region.

    Abstract translation: 一种用于在半导体结构的含锗接触区域上形成接触的方法，所述方法包括以下步骤：提供所述半导体结构，包括：（i）含Ge接触区域，（ii）任选的SiO 2层涂层 所述含Ge接触区域，（iii）涂覆所述SiO 2层（如果存在）或所述含Ge接触区域的Si 3 N 4层; 通过电感耦合等离子体选择性地蚀刻Si 3 N 4层，从而暴露下面的SiO 2层（如果存在）或含Ge接触区域; 选择性地蚀刻SiO 2层（如果存在），从而暴露SiGe：B接触区域; 以及在所述含Ge接触区域上产生所述接触。

    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure
    15.
    发明申请
    Method for Forming a Transistor Structure Comprising a Fin-Shaped Channel Structure 有权
    形成包括鳍形通道结构的晶体管结构的方法

    公开(公告)号：US20160126131A1

    公开(公告)日：2016-05-05

    申请号：US14924832

    申请日：2015-10-28

    Applicant: IMEC VZW

    Inventor： Nadine Collaert ,  Geert Eneman ,  Naoto Horiguchi ,  Min-Soo Kim ,  Rita Rooyackers ,  Anabela Veloso ,  Liesbeth Witters

    IPC: H01L21/762 ,  H01L21/3205 ,  H01L29/06 ,  H01L21/32

    CPC classification number: H01L21/76224 ,  H01L21/32 ,  H01L21/32055 ,  H01L29/0649 ,  H01L29/42392 ,  H01L29/66742 ,  H01L29/78696

    Abstract: An example method includes providing a layer stack in a trench defined by adjacent STI structures and recessing the STI structures adjacent to the layer stack to thereby expose an upper portion of the layer stack, the upper portion comprising at least a channel portion. The method further includes providing one or more protection layers on the upper portion of the layer stack and then further recessing the STI structures selectively to the protection layers and the layer stack, to thereby expose a central portion of the layer stack. And the method includes removing the central portion of the layer stack, resulting in a freestanding upper part and a lower part of the layer stack being physically separated from each other.

    Abstract translation: 一个示例性方法包括在由相邻STI结构限定的沟槽中提供层堆叠，并使邻近层堆叠的STI结构凹陷，从而暴露层堆叠的上部，上部至少包括沟道部分。 该方法还包括在层堆叠的上部提供一个或多个保护层，然后进一步将STI结构选择性地凹入保护层和层堆叠，从而暴露层堆叠的中心部分。 并且该方法包括去除层堆叠的中心部分，导致层叠体的独立上部和下部在物理上彼此分离。

    LOW PARASITIC Ccb HETEROJUNCTION BIPOLAR TRANSISTOR
    17.
    发明申请
    LOW PARASITIC Ccb HETEROJUNCTION BIPOLAR TRANSISTOR 有权

    公开(公告)号：US20210167187A1

    公开(公告)日：2021-06-03

    申请号：US17103031

    申请日：2020-11-24

    Applicant: IMEC VZW

    Inventor： Abhitosh Vais ,  Liesbeth Witters ,  Yves Mols

    IPC: H01L29/66 ,  H01L29/737 ,  H01L29/08

    Abstract: A method for fabricating a heterojunction bipolar transistor (HBT) comprises providing a semiconductor support layer and forming an even number of at least four elongated wall structures on the support layer. The wall structures are arranged side-by-side at a regular interval. An odd number of at least three semiconductor collector-material ridge structures are formed on the support layer. Each ridge structure is formed between two adjacent wall structures. A semiconductor base-material layer is formed on a determined ridge structure of the at least three ridge structures. A semiconductor emitter-material layer is formed on the base-material layer. The base-material layer is epitaxially extended so that it coherently covers all the wall structures and all the ridge structures. All the ridge structures except for the determined ridge structure are selectively removed.

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