-
公开(公告)号：US11533824B2
公开(公告)日：2022-12-20
申请号：US17346841
申请日：2021-06-14
Applicant: Infineon Technologies AG
Inventor： Regina Nottelmann , Andre Arens , Michael Ebli , Alexander Herbrandt , Ulrich Michael Georg Schwarzer , Alparslan Takkac
Abstract: A method for producing a power semiconductor module arrangement includes: arranging a semiconductor substrate in a housing, the housing including a through hole extending through a component of the housing; inserting a pin or bolt into the through hole such that an upper end of the pin/bolt is not inserted into the through hole; arranging a printed circuit board on the housing; arranging the housing on a heat sink having a hole, the housing being arranged on the heat sink such that the through hole is aligned with the hole in the heat sink; and by way of a first pressing tool, exerting a force on a defined contact area of the printed circuit board and pressing the pin/bolt into the hole in the heat sink, wherein the defined contact area is arranged directly above the pin/bolt.
-
公开(公告)号：US09668350B2
公开(公告)日：2017-05-30
申请号：US14709605
申请日：2015-05-12
Applicant: Infineon Technologies AG
Inventor： Andre Arens
IPC: H05K1/18 , H01L25/07 , H01L23/538 , H01L23/495 , H01L23/498
CPC classification number: H05K1/185 , H01L23/4952 , H01L23/49541 , H01L23/49575 , H01L23/49844 , H01L23/5386 , H01L23/5389 , H01L25/072 , H01L2924/0002 , H05K2201/10507 , H01L2924/00
Abstract: A semiconductor module includes a printed circuit board, and first and second embedded semiconductor chips. The first and second semiconductor chips each have a first load connection and a second load connection. The printed circuit board further includes a structured first metalization layer, which has a first section and a second section, and a structured second metalization layer, which has a first section, a second section and a third section. The first section of the second metalization layer and the second section of the first metalization layer have comb shaped structures having first and second protrusions. These first and second sections are electrically conductively connected to one another by a number of first plated-through holes each of which is permanently electrically conductively connected both at first protrusions to the first section of the second metalization layer and at second protrusions to the second section of the first metalization layer.
-
公开(公告)号：US20230326823A1
公开(公告)日：2023-10-12
申请号：US17714550
申请日：2022-04-06
Applicant: Infineon Technologies AG
Inventor： Andre Arens , Michael Ebli
CPC classification number: H01L23/34 , H01L23/053 , G01K1/14 , G01K1/16 , G01J5/0007 , G01J5/0205
Abstract: A semiconductor module includes a first circuit carrier including one or more heat generating elements mounted on an upper surface of the first circuit carrier, a second circuit carrier mounted over the first circuit carrier and being vertically spaced apart from the upper surface of the first circuit carrier, and a temperature sensor that is fixedly attached to the second circuit carrier and is arranged in a vertical space between the lower surface of the second circuit carrier and the upper surface of the first circuit carrier, wherein the temperature sensor is arranged in sufficient proximity to a first one of the heat generating elements to obtain a direct temperature measurement from the first one of the heat generating elements.
-
公开(公告)号：US11378614B2
公开(公告)日：2022-07-05
申请号：US17009718
申请日：2020-09-01
Applicant: Infineon Technologies AG
Inventor： Jens Barrenscheen , Andre Arens
Abstract: This disclosure is directed to circuits and techniques for detecting or responding to temperature of a power switch. A driver circuit for the power switch may be configured to deliver a modulation signal to a control node of the power switch to control on/off switching of the power switch, wherein the driver circuit is further configured to modulate an output impedance of the driver circuit at the control node, perform one or more voltage measurements while modulating the output impedance of the driver circuit, and control the power switch based at least in part on the one or more voltage measurements.
-
公开(公告)号：US09924594B2
公开(公告)日：2018-03-20
申请号：US14499915
申请日：2014-09-29
Applicant: Infineon Technologies AG
Inventor： Andre Arens , Juergen Hoegerl , Magdalena Hoier
IPC: H05K7/10 , H05K7/12 , H05K1/11 , H01L21/56 , H01L25/18 , H01L25/00 , H05K1/18 , H05K1/02 , H05K3/28 , H05K7/14 , H05K1/14 , H01L23/31
CPC classification number: H05K1/111 , H01L21/56 , H01L23/3121 , H01L25/18 , H01L25/50 , H01L2224/48091 , H01L2224/48137 , H01L2924/13055 , H01L2924/181 , H05K1/0256 , H05K1/144 , H05K1/181 , H05K3/28 , H05K3/284 , H05K7/1432 , H05K2201/0104 , H05K2201/042 , H05K2201/10303 , H05K2201/10318 , H01L2924/00014 , H01L2924/00 , H01L2924/00012
Abstract: A printed circuit board (PCB) has a first, structured metalization arranged on its top side and at least one second metalization arranged below the first metalization in a vertical direction, parallel to the first metalization and insulated therefrom. Also on the PCB top side is a bare semiconductor chip having contact electrodes connected by bonding wires to corresponding contact pads of the first metalization on the PCB top side. A first portion of the contact electrodes and corresponding contact pads carry high voltage during operation. All high-voltage-carrying contact pads are conductively connected to the second metalization via plated-through holes. An insulation layer completely covers the chip and a delimited region of the PCB around the chip, and all high-voltage-carrying contact pads and the plated-through holes are completely covered by the insulation layer. A second portion of the contact electrodes and corresponding contact pads are under low voltages during operation.
-
Patent Agency Ranking
公开(公告)号：US09888563B2
公开(公告)日：2018-02-06
申请号：US15261080
申请日：2016-09-09
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer , Andre Arens
CPC classification number: H05K1/0231 , H02M1/44 , H02M7/003 , H02M2001/123 , H05K1/0203 , H05K1/0204 , H05K1/181 , H05K1/185 , H05K2201/10015
Abstract: An electronics assembly includes a plurality of first semiconductor chips each having a first load terminal and a second load terminal, a conductor structure having a first conductor strip, a second conductor strip and a third conductor strip, a plurality of first interference-suppression capacitors arranged on the conductor structure and each having a first capacitor terminal and a second capacitor terminal, and a heat sink. The first load terminal of each first semiconductor chip is electrically connected to the first conductor strip, the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip, the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first conductor strip, the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second conductor strip, and the heat sink is electrically connected to the second conductor strip.
-
公开(公告)号：US20170079132A1
公开(公告)日：2017-03-16
申请号：US15261080
申请日：2016-09-09
Applicant: Infineon Technologies AG
Inventor： Reinhold Bayerer , Andre Arens
CPC classification number: H05K1/0231 , H02M1/44 , H02M7/003 , H02M2001/123 , H05K1/0203 , H05K1/0204 , H05K1/181 , H05K1/185 , H05K2201/10015
Abstract: An electronics assembly includes a plurality of first semiconductor chips each having a first load terminal and a second load terminal, a conductor structure having a first conductor strip, a second conductor strip and a third conductor strip, a plurality of first interference-suppression capacitors arranged on the conductor structure and each having a first capacitor terminal and a second capacitor terminal, and a heat sink. The first load terminal of each first semiconductor chip is electrically connected to the first conductor strip, the second load terminal of each first semiconductor chip is electrically connected to the third conductor strip, the first capacitor terminal of each first interference-suppression capacitor is electrically connected to the first conductor strip, the second capacitor terminal of each first interference-suppression capacitor is electrically connected to the second conductor strip, and the heat sink is electrically connected to the second conductor strip.
Abstract translation: 电子组件包括多个第一半导体芯片，每个第一半导体芯片具有第一负载端子和第二负载端子，具有第一导体条，第二导体条和第三导体条的导体结构，多个第一干涉抑制电容器， 在导体结构上，每个具有第一电容器端子和第二电容器端子，以及散热器。 每个第一半导体芯片的第一负载端子电连接到第一导体条，每个第一半导体芯片的第二负载端子电连接到第三导体条，每个第一干涉抑制电容器的第一电容器端子电连接 对于第一导体条，每个第一干涉抑制电容器的第二电容器端子电连接到第二导体条，并且散热器电连接到第二导体条。
-
公开(公告)号：US08994413B2
公开(公告)日：2015-03-31
申请号：US13871288
申请日：2013-04-26
Applicant: Infineon Technologies AG
Inventor： Peter Kanschat , Andre Arens , Hartmut Jasberg , Ulrich Schwarzer
CPC classification number: H03K17/00 , H03K17/163 , H03K17/168
Abstract: A method for driving a controllable power semiconductor switch, having a first input terminal and first and second output terminals coupled to a voltage supply and a load, the first and second output terminals providing an output of the power semiconductor switch, includes adjusting a gradient of switch-off edges of an output current and an output voltage of the power semiconductor switch by a voltage source arrangement coupled to the input terminal. A gradient of switch-on edges of an output current and an output voltage is adjusted by a controllable current source arrangement that is coupled to the input terminal and generates a gate drive current. The profile of the gate drive current from one switching operation to a subsequent switching operation, beginning at a rise in the output current and ending at a decrease in the output voltage, is varied at most within a predefined tolerance band.
Abstract translation: 一种用于驱动可控功率半导体开关的方法，具有第一输入端和耦合到电压源和负载的第一和第二输出端，提供功率半导体开关的输出的第一和第二输出端包括： 通过耦合到输入端的电压源装置，输出电流的关断边缘和功率半导体开关的输出电压。 输出电流和输出电压的接通边沿的梯度由耦合到输入端子的可控电流源装置调节并产生栅极驱动电流。 从输出电流的上升开始并以输出电压的降低结束的栅极驱动电流从一个开关操作到随后的开关操作的曲线最多在预定义的公差带内变化。
-
19.发明公开公开(公告)号：US20230369187A1
公开(公告)日：2023-11-16
申请号：US18314459
申请日：2023-05-09
Applicant: Infineon Technologies AG
Inventor： Andre Arens , Jens de Bock , Xi Zhang , Dietmar Spitzer
CPC classification number: H01L23/49811 , H01L25/072 , H01L21/56 , H01L23/3121 , H01L23/49838 , H05K1/181 , H05K1/0213 , H05K2201/10151 , H05K2201/083
Abstract: A power semiconductor module arrangement includes: a housing; a substrate having a substrate layer and a first metallization layer on a first side of the substrate layer, inside the housing or forming a bottom of the housing; a printed circuit board inside the housing, vertically above and in parallel to the substrate; electrically conducting components on the printed circuit board and substrate; an encapsulant at least partly filling the interior of the housing; and a magnetic field sensor either on the substrate within range of a magnetic field caused by a current flowing through one of the electrically conducting components arranged on the printed circuit board, or on the printed circuit board within range of a magnetic field caused by a current flowing through one of the electrically conducting components arranged on the substrate. The magnetic field sensor is electrically insulated from the respective electrically conducting component.
-
20.发明公开公开(公告)号：US20230253291A1
公开(公告)日：2023-08-10
申请号：US18101608
申请日：2023-01-26
Applicant: Infineon Technologies AG
Inventor： Matthias Lassmann , Andre Arens , Marco Ludwig , Guido Bönig
IPC: H01L23/42 , H01L23/373 , H01L23/31 , H01L23/498 , H01L25/07 , H01L21/56
CPC classification number: H01L23/42 , H01L23/3737 , H01L23/3121 , H01L23/49811 , H01L23/315 , H01L25/072 , H01L23/49833 , H01L23/49844 , H01L21/56 , H01L2924/182 , H01L2924/13055 , H01L2224/32225 , H01L24/48
Abstract: A power semiconductor module arrangement includes a housing, a substrate arranged inside the housing, a printed circuit board arranged inside the housing distant from and in parallel to the substrate, an encapsulant at least partly filling the interior of the housing and covering the substrate and the printed circuit board, and a heat protective layer arranged inside the housing between the substrate and the printed circuit board, and extending in a plane that is parallel to the substrate and the printed circuit board. A thermal resistance of the heat protective layer is greater than a thermal resistance of the encapsulant.
-
-
-
-
-
-
-
-
-
Search Results
25
records
(took 0.016 seconds)
