公开(公告)号：US09805790B2

公开(公告)日：2017-10-31

申请号：US15025229

申请日：2013-12-05

Applicant: Intel Corporation

Inventor： Nathaniel J. August ,  Pulkit Jain ,  Stefan Rusu ,  Fatih Hamzaoglu ,  Rangharajan Venkatesan ,  Muhammad Khellah ,  Charles Augustine ,  Carlos Tokunaga ,  James W. Tschanz ,  Yih Wang

IPC: G11C13/00 ,  G11C14/00 ,  G11C11/16

CPC classification number: G11C13/0061 ,  G11C11/161 ,  G11C11/1657 ,  G11C11/1659 ,  G11C11/1675 ,  G11C11/1693 ,  G11C13/0011 ,  G11C13/0014 ,  G11C14/0081 ,  G11C14/009

Abstract: Described is an apparatus including memory cell with retention using resistive memory. The apparatus comprises: memory element including a first inverting device cross-coupled to a second inverting device; a restore circuit having at least one resistive memory element, the restore circuit coupled to an output of the first inverting device; a third inverting device coupled to the output of the first inverting device; a fourth inverting device coupled to an output of the third inverting device; and a save circuit having at least one resistive memory element, the save circuit coupled to an output of the third inverting device.

公开(公告)号：US20160294394A1

公开(公告)日：2016-10-06

申请号：US15182486

申请日：2016-06-14

Applicant: INTEL CORPORATION

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

Abstract translation: 实施例包括用于在低电压域和高电压域之间电压移位数据信号的装置，方法和系统。 在实施例中，电压电平移位器电路可以包括自适应保持器电路，增强的可中断电源电路和/或电容升压电路，以减小由电压电平移位器电路支持的低电压域的最小电压。 可以描述和要求保护其他实施例。

公开(公告)号：US12237832B2

公开(公告)日：2025-02-25

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/177 ,  G01R31/28 ,  H03K19/0175 ,  H03K19/0185 ,  H03K19/17768 ,  H03K19/17784

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US20240005962A1

公开(公告)日：2024-01-04

申请号：US17856897

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Minki Cho ,  Daniel Nemiroff ,  Carlos Tokunaga ,  James W. Tschanz ,  Kah Meng Yeem ,  Yaxin Shui

IPC: G11C5/00

CPC classification number: G11C5/005

Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

公开(公告)号：US11828776B2

公开(公告)日：2023-11-28

申请号：US16829582

申请日：2020-03-25

Applicant: Intel Corporation

Inventor： Pratik Patel ,  Sriram Vangal ,  Patrick Koeberl ,  Miguel Bautista Gabriel ,  James Tschanz ,  Carlos Tokunaga

IPC: G01R19/165 ,  G06F21/75 ,  H03K5/00 ,  H03K3/037 ,  H03K19/21 ,  H01L23/00 ,  G06F11/07

CPC classification number: G01R19/16533 ,  G06F11/0736 ,  G06F11/0757 ,  G06F11/0772 ,  G06F21/755 ,  H01L23/576 ,  H03K3/037 ,  H03K5/00 ,  H03K19/21 ,  H03K2005/00058 ,  H03K2005/00078

Abstract: A voltage detection circuit includes a tunable delay circuit that receives a supply voltage and that generates a delayed signal in response to an input signal. A control circuit causes a first adjustment in a delay provided by the tunable delay circuit to the delayed signal. An error detection circuit generates an error indication in an error signal in response to a change in a timing of the delayed signal relative to a clock signal caused by the first adjustment in the delay provided to the delayed signal. The control circuit causes a second adjustment in the delay provided by the tunable delay circuit to the delayed signal in response to the error indication. The error detection circuit causes the error signal to be indicative of the supply voltage reaching a threshold voltage after the second adjustment in the delay.

公开(公告)号：US20180191347A1

公开(公告)日：2018-07-05

申请号：US15394296

申请日：2016-12-29

Applicant: INTEL CORPORATION

Inventor： Andrea Bonetti ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Minki Cho ,  Pascal A. Meinerzhagen ,  Muhammad M. Khellah

IPC: H03K19/0185 ,  H03K19/21

CPC classification number: H03K19/018521 ,  H03K19/21

Abstract: Embodiments include circuits, apparatuses, and systems for voltage level shifter monitors. In embodiments, a voltage level shifter monitor may include a first signal generator to generate a signal in a first voltage domain, a second signal generator to generate a second signal in a second voltage domain, where the second digital signal corresponds to the first digital signal, a voltage level shifter replica circuit to convert the first digital signal from the first voltage domain to a third digital signal in the second voltage domain, and a comparison circuit to generate a digital error signal based at least in part on the second digital signal and the third digital signal. Other embodiments may be described and claimed.

公开(公告)号：US20160149579A1

公开(公告)日：2016-05-26

申请号：US14553934

申请日：2014-11-25

Applicant: Intel Corporation

Inventor： Amit R. Trivedi ,  Jaydeep P. Kulkarni ,  Carlos Tokunaga ,  Muhammad M. Khellah ,  James W. Tschanz

IPC: H03K19/0185

CPC classification number: H03K19/018521 ,  H03K3/356113

Abstract: Embodiments include apparatuses, methods, and systems for voltage level shifting a data signal between a low voltage domain and a high voltage domain. In embodiments, a voltage level shifter circuit may include adaptive keeper circuitry, enhanced interruptible supply circuitry, and/or capacitive boosting circuitry to reduce a minimum voltage of the low voltage domain that is supported by the voltage level shifter circuit. Other embodiments may be described and claimed.

公开(公告)号：US12243611B2

公开(公告)日：2025-03-04

申请号：US17856897

申请日：2022-07-01

Applicant: Intel Corporation

Inventor： Minki Cho ,  Daniel Nemiroff ,  Carlos Tokunaga ,  James W. Tschanz ,  Kah Meng Yeem ,  Yaxin Shui

IPC: G11C5/00

Abstract: An integrated circuit (IC) die comprises a sensor, which includes a pulse generator and a pulse expander. The pulse generator comprises gate circuits coupled to each other in an in-series arrangement. An input of the pulse generator is coupled to receive a voltage and the pulse generator is to generate a first signal based on the voltage. The pulse generator is to generate a first pulse of the first signal based on an event wherein radiation from a laser is incident upon the pulse generator. The pulse expander is coupled to receive the first signal from the pulse generator and to generate a second signal based on the first signal, wherein a second pulse of the second signal is based on the first pulse. A first duration of the first pulse is less than a second duration of the second pulse.

公开(公告)号：US20220006459A1

公开(公告)日：2022-01-06

申请号：US17479963

申请日：2021-09-20

Applicant: Intel Corporation

Inventor： Miguel Bautista Gabriel ,  Sriram Vangal ,  Patrick Koeberl ,  Pratik Patel ,  Muhammad Khellah ,  James Tschanz ,  Carlos Tokunaga ,  Suyoung Bang

IPC: H03K19/17768 ,  H03K19/17784 ,  H03K19/0185 ,  H03K19/0175 ,  G01R31/28

Abstract: A detection circuit includes a tunable delay circuit that generates a delayed signal and that receives a supply voltage. The detection circuit includes a control circuit that adjusts a delay provided by the tunable delay circuit to the delayed signal. The detection circuit includes a time-to-digital converter circuit that converts the delay provided by the tunable delay circuit to the delayed signal to a digital code and adjusts the digital code based on changes in the supply voltage. The control circuit causes the tunable delay circuit to maintain the delay provided to the delayed signal constant in response to the digital code reaching an alignment value. The detection circuit may continuously monitor timing margin of a data signal relative to a clock signal and update the digital code in every clock cycle. The detection circuit may be a security sensor that detects changes in the supply voltage.

公开(公告)号：US10122347B2

公开(公告)日：2018-11-06

申请号：US15477913

申请日：2017-04-03

Applicant: Intel Corporation

Inventor： Minki Cho ,  Jaydeep Kulkarni ,  Carlos Tokunaga ,  Muhammad Khellah ,  James Tschanz

IPC: G11C7/00 ,  G11C7/12 ,  H03K3/011 ,  H03K3/012 ,  G11C11/419 ,  G06F1/32

Abstract: An apparatus is provided which includes: a first power supply node; a second power supply node; a memory bit-cell coupled to the second power supply node; a circuitry coupled to the first and second power supply nodes, the circuitry to operate in a diode-connected mode; and a transistor coupled in parallel to the circuitry, wherein the transistor is controllable by a digital signal such that when the transistor is to turn on, it is to apply voltage and/or current stress to the memory bit-cell.