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公开(公告)号：US20210352807A1
公开(公告)日：2021-11-11
申请号：US17383084
申请日：2021-07-22
Applicant: INTEL CORPORATION
Inventor： Eric Li , Kemal Aygun , Kai Xiao , Gong Ouyang , Zhichao Zhang
Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure on a low density interconnect (LDI) printed circuit board (PCB) according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region within the conductive structure. Other embodiments are described and claimed.
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公开(公告)号：US11089689B2
公开(公告)日：2021-08-10
申请号：US16081487
申请日：2016-04-02
Applicant: INTEL CORPORATION
Inventor： Eric Li , Kemal Aygun , Kai Xiao , Gong Ouyang , Zhichao Zhang
Abstract: Fine feature formation techniques for printed circuit boards are described. In one embodiment, for example, a method may comprise fabricating a conductive structure 306 on a low density interconnect (LDI) printed circuit board (PCB) 150 according to an LDI fabrication process and forming one or more fine conductive features on the LDI PCB by performing a fine feature formation (FFF) process, the FFF process to comprise removing conductive material of the conductive structure along an excision path to form a fine gap region 308 within the conductive structure. Other embodiments are described and claimed.
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公开(公告)号：US10249924B2
公开(公告)日：2019-04-02
申请号：US14752642
申请日：2015-06-26
Applicant: Intel Corporation
Inventor： Kai Xiao , Raul Enriquez Shibayama , Gong Ouyang , Jose Diego Guillen Gonzalez , Beom-Taek Lee
Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
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公开(公告)号：US20180174940A1
公开(公告)日：2018-06-21
申请号：US15383858
申请日：2016-12-19
Applicant: Intel Corporation
Inventor： Shelby Ferguson , Gong Ouyang , Russell S. Aoki , Zhichao Zhang , Kai Xiao
IPC: H01L23/34 , H01L23/373 , H01L23/498
CPC classification number: H01L23/345 , H01L23/49816 , H01L23/49838 , H01L2224/16225
Abstract: Disclosed herein are fine-featured traces for integrated circuit (IC) package support structures, and related systems, devices, and methods. For example, a device may include a printed circuit board (PCB) having an insulating material and a heater trace on the insulating material. In some embodiments, the heater trace may have a section with a width less than 3.5 mils. In some embodiments, a section of the heater trace may be adjacent to a burned portion of the insulating material.
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Patent Agency Ranking
公开(公告)号：US09935353B2
公开(公告)日：2018-04-03
申请号：US14862159
申请日：2015-09-23
Applicant: Intel Corporation
Inventor： Gong Ouyang , Shaowu Huang , Kai Xiao
CPC classification number: H01P3/081 , H01P3/04 , H01P11/003 , H05K1/024 , H05K1/0243 , H05K1/0245 , H05K2201/09036 , H05K2201/09872
Abstract: A conductor in a laminar structure, such as a printed circuit board or thin-film stack, is closely flanked by at least one open trench filled with an ambient medium (e.g., air, another gas, vacuum) of a lower dielectric loss than the conductor's surrounding dielectric. The trench may be made by any suitably precise method such as laser scribing, chemical etching or mechanical displacement. A thin layer of dielectric may be left on the sides of the conductor to prevent oxidation or other reactions that may reduce conductivity. When the conductor carries a signal, part of an electric and/or magnetic field that would ordinarily travel through the surrounding dielectric encounters the low-loss ambient medium (e.g. air) in the trench. The effective dielectric loss surrounding the conductor is lowered, reducing signal attenuation and crosstalk, particularly at high frequencies.
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公开(公告)号：US09922751B2
公开(公告)日：2018-03-20
申请号：US15088924
申请日：2016-04-01
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Gong Ouyang , Kai Xiao , Eric J. Li , Kemal Aygun
CPC classification number: H01B7/0241 , H01B11/1856 , H01B11/20 , H01B13/08 , H01B13/22 , H05K9/0098
Abstract: A helically wound insulated twinax cable reduces cable dielectric loss by increasing the percentage of air in the dielectric filler surrounding the signal conductors. The helical insulator wire winding further provides mechanical support and reduces the risk of creating an electrical short-circuit. This will improve differential signaling capability of the two-conductor cable and enable longer cable range.
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公开(公告)号：US09791899B2
公开(公告)日：2017-10-17
申请号：US14968698
申请日：2015-12-14
Applicant: Intel Corporation
Inventor： Gong Ouyang , Kai Xiao , Lu-Vong Phan
CPC classification number: G06F1/185 , G06F1/1616 , G06F1/1637 , G06F1/1681 , H05K1/029 , H05K1/181 , H05K3/222 , H05K2201/10159 , Y02P70/611
Abstract: An apparatus and method to permit reconfiguration of a memory topology. A printed circuit board (PCB) has a central processing unit (CPU) connector coupled a pair of dual inline memory module (DIMM) connectors coupled thereto. The PCB defines an electrical access channel coupling the pair of DIMM connectors into a T topology having a first branch and a second branch. The second branch of the T topology is electrically discontinuous with the rest of the T topology proximate to a T junction. A bridge may be provided to span the discontinuity.
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公开(公告)号：US20160378215A1
公开(公告)日：2016-12-29
申请号：US14752642
申请日：2015-06-26
Applicant: INTEL CORPORATION
Inventor： Kai Xiao , Raul Enriquez Shibayama , Gong Ouyang , Jose Diego Guillen Gonzalez , Beom-Taek Lee
CPC classification number: H01P3/08 , H01P5/028 , H05K1/0251 , H05K1/116 , H05K3/403 , H05K3/429 , H05K2201/09645 , H05K2201/09854
Abstract: Techniques and mechanisms to provide a compact arrangement of vias extending through at least a portion of a printed circuit board (PCB) or other substrate. In an embodiment, the substrate includes a dielectric material and a sidewall structure forming a hole region that extends at least partially through the dielectric material. The hole region adjoins each of a first via and a second via, and is also located between the first via and second via. In another embodiment, the first via is coupled to exchange a first signal of a differential signal pair, and the second via is coupled to exchange a second signal of the same differential signal pair.
Abstract translation: 提供延伸穿过印刷电路板（PCB）或其它基板的至少一部分的通孔的紧凑布置的技术和机构。 在一个实施例中，衬底包括电介质材料和形成至少部分延伸穿过电介质材料的孔区的侧壁结构。 孔区域邻接第一通孔和第二通孔中的每一个，并且还位于第一通孔和第二通孔之间。 在另一个实施例中，第一通孔被耦合以交换差分信号对的第一信号，并且第二通孔被耦合以交换相同差分信号对的第二信号。
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公开(公告)号：US20160276092A1
公开(公告)日：2016-09-22
申请号：US14678714
申请日：2015-04-03
Applicant: Intel Corporation
Inventor： Zhichao Zhang , Gong Ouyang , Kai Xiao , Kemal Aygun , Beom-Taek Lee
CPC classification number: H05K1/0237 , H01F17/0013 , H01F2017/002 , H05K1/0233 , H05K1/116 , H05K1/165
Abstract: Systems, apparatuses, and methods may include a circuit board having a plated through hole with a via portion and a stub portion and a self-coupled inductor electrically coupled to the via portion of the plated through hole. The self-coupled inductor may include a first inductor mutually coupled to a second inductor in series to reduce a capacitive effect of the stub portion of the plated through hole.
Abstract translation: 系统，装置和方法可以包括具有电镀通孔的电路板，其具有通孔部分和短截线部分，以及电耦合到电镀通孔的通孔部分的自耦合电感器。 自耦合电感器可以包括串联耦合到第二电感器的第一电感器，以减小电镀通孔的短截线部分的电容效应。
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