公开(公告)号：US11373995B2

公开(公告)日：2022-06-28

申请号：US16643928

申请日：2017-09-29

Applicant: INTEL CORPORATION

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/778 ,  H01L27/02 ,  H01L21/8252 ,  H01L27/06 ,  H01L29/20 ,  H01L29/205 ,  H01L29/47 ,  H01L29/66 ,  H01L29/872 ,  H01L27/07

Abstract: A Group III-Nitride (III-N) device structure is presented comprising: a heterostructure having three or more layers comprising III-N material, a cathode comprising donor dopants, wherein the cathode is on a first layer of the heterostructure,
an anode within a recess that extends through two or more of the layers of the heterostructure, wherein the anode comprises a first region wherein the anode is separated from the heterostructure by a high k dielectric material, and a second region wherein the anode is in direct contact with the heterostructure, and a conducting region in the first layer in direct contact to the cathode and conductively connected to the anode. Other embodiments are also disclosed and claimed.

公开(公告)号：US09515049B2

公开(公告)日：2016-12-06

申请号：US14368434

申请日：2013-12-19

Applicant: Intel Corporation

Inventor： Sven Albers ,  Michael Skinner ,  Hans-Joachim Barth ,  Peter Baumgartner ,  Harald Gossner

IPC: H01L25/065 ,  H01L23/552 ,  H01L23/522 ,  H01L29/06 ,  H01L23/00 ,  H01L27/02

CPC classification number: H01L25/0652 ,  H01L23/367 ,  H01L23/3675 ,  H01L23/5226 ,  H01L23/5227 ,  H01L23/552 ,  H01L23/562 ,  H01L23/564 ,  H01L23/66 ,  H01L24/13 ,  H01L24/16 ,  H01L24/17 ,  H01L24/48 ,  H01L24/49 ,  H01L24/81 ,  H01L24/85 ,  H01L25/065 ,  H01L25/0657 ,  H01L27/0207 ,  H01L29/0657 ,  H01L2223/6677 ,  H01L2224/131 ,  H01L2224/1319 ,  H01L2224/16105 ,  H01L2224/16113 ,  H01L2224/16225 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/481 ,  H01L2224/48106 ,  H01L2224/4813 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48225 ,  H01L2224/48227 ,  H01L2224/48482 ,  H01L2224/49 ,  H01L2224/73257 ,  H01L2224/81001 ,  H01L2224/81007 ,  H01L2224/8114 ,  H01L2224/81801 ,  H01L2224/8185 ,  H01L2224/85801 ,  H01L2225/06506 ,  H01L2225/0651 ,  H01L2225/06551 ,  H01L2225/06589 ,  H01L2924/00014 ,  H01L2924/19104 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014 ,  H01L2924/00012

Abstract: Embodiments of a flexibly-wrapped integrated circuit die device and a method for mounting a flexibly-wrapped integrated circuit die to a substrate are disclosed. In some embodiments, the flexibly-wrapped integrated circuit die device includes a substrate and a flexible integrated circuit die coupled to the substrate in a substantially vertical orientation with reference to a surface of the substrate.

Abstract translation: 公开了一种柔性包裹的集成电路管芯器件的实施例和用于将柔性封装的集成电路管芯安装到衬底的方法。 在一些实施例中，柔性包裹的集成电路管芯器件包括基板和柔性集成电路管芯，所述基板和基板相对于基板的表面以基本垂直的取向联接到基板。

公开(公告)号：US20250006668A1

公开(公告)日：2025-01-02

申请号：US18342112

申请日：2023-06-27

Applicant: Intel Corporation

Inventor： Carla Moran Guizan ,  Peter Baumgartner ,  Michael Langenbuch ,  Mamatha Yakkegondi Virupakshappa ,  Jonathan Jensen ,  Roshini Sachithanandan ,  Philipp Riess

IPC: H01L23/66 ,  H01L23/528

Abstract: Waveguide structures are built into integrated circuit devices using standard processing steps for semiconductor device fabrication. A waveguide may include a base, a top, and two side walls. At least one of the walls (e.g., the base or the top) may be formed in a metal layer. The base or top may be patterned to provide a transition to a planar transmission line, such as a coplanar waveguide. The side walls may be formed using vias.

公开(公告)号：US20240429888A1

公开(公告)日：2024-12-26

申请号：US18212308

申请日：2023-06-21

Applicant: Intel Corporation

Inventor： Ritesh Bhat ,  Steven Callender ,  Peter Baumgartner

IPC: H03F3/45 ,  H03G1/00 ,  H03G3/00

Abstract: An integrated circuit device includes a variable gain amplifier with multiple gain circuits coupled in parallel, where one or more of the multiple gain circuits comprises a first differential pair of transistors, and a complementarily switched second differential pair of transistors cross-connected to the first differential pair of transistors with a sign inversion relative to the first differential pair of transistors. Other examples are disclosed and claimed.

公开(公告)号：US20230252214A1

公开(公告)日：2023-08-10

申请号：US17666616

申请日：2022-02-08

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Carla Moran Guizan ,  Peter Baumgartner ,  Richard Geiger ,  Alexander Bechtold ,  Uwe Hodel ,  Walther Lutz ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: G06F30/392 ,  H01L27/02

CPC classification number: G06F30/392 ,  H01L27/0207

Abstract: Methods for providing fill patterns for IC devices are disclosed. An example method includes detecting a first device and a second device in an image, e.g., a two- or three-dimensional image representing the IC device. A line is defined based on the devices. The line divides the image into a first section and a second section. A first structure is generated based on the first device. A second structure is generated based on the second device. The second structure is a mirror image of the first structure across the line. A first fill pattern is generated in the first section based on the first structure. A second fill pattern is generated in the second section based on the first fill pattern, e.g., through a reflection transformation of the first fill pattern across the line. The two fill patterns represent patterns of fill structures to be included in the IC device.

公开(公告)号：US20220320350A1

公开(公告)日：2022-10-06

申请号：US17848275

申请日：2022-06-23

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger ,  Han Wui Then ,  Marko Radosavljevic ,  Sansaptak Dasgupta

IPC: H01L29/93 ,  H01L29/06 ,  H01L29/20 ,  H01L29/778

Abstract: A variable capacitance III-N device having multiple two-dimensional electron gas (2DEG) layers are described. In some embodiments, the device comprises a first source and a first drain; a first polarization layer adjacent to the first source and the first drain; a first channel layer coupled to the first source and the first drain and adjacent to the first polarization layer, the first channel layer comprising a first 2DEG region; a second source and a second drain; a second polarization layer adjacent to the second source and the second drain; and a second channel layer coupled to the second source and the second drain and adjacent to the second polarization layer, the second channel layer comprising a second 2DEG region, wherein the second channel layer is over the first polarization layer.

公开(公告)号：US11201151B2

公开(公告)日：2021-12-14

申请号：US16833094

申请日：2020-03-27

Applicant: Intel Corporation

Inventor： Richard Hudeczek ,  Philipp Riess ,  Richard Geiger ,  Peter Baumgartner

IPC: H01L27/088 ,  H01L29/423 ,  H01L29/78 ,  H01L29/06

Abstract: Embodiments disclosed herein include resonators, such as resonant fin transistors (RFTs). In an embodiment a resonator comprises a substrate, a set of contact fins over the substrate, a first contact proximate to a first end of the set of contact fins, and a second contact proximate to a second end of the set of contact fins. In an embodiment, the resonator further comprises a set of skip fins over the substrate and adjacent to the set of contact fins. In an embodiment, the resonator further comprises a gate electrode over the set of contact fins and the set of skip fins, wherein the gate electrode is between the first contact and the second contact.

公开(公告)号：US20240322775A1

公开(公告)日：2024-09-26

申请号：US18187001

申请日：2023-03-21

Applicant: Intel Corporation

Inventor： Telesphor Kamgaing ,  Peter Baumgartner ,  Steven Callender ,  Richard Geiger ,  Harald Gossner ,  Jonathan Jensen

IPC: H03F3/60 ,  H01L23/66 ,  H03F3/195 ,  H03F3/24

CPC classification number: H03F3/602 ,  H01L23/66 ,  H03F3/195 ,  H03F3/245 ,  H01L2223/6677 ,  H03F2200/294 ,  H03F2200/451

Abstract: Disclosed herein are electronic assemblies, integrated circuit (IC) packages, and communication devices implementing three-dimensional power combiners. An electronic assembly may include a first die, comprising a first transmission line, and a second die, comprising a second transmission line. Each die includes a first face and an opposing second face, and the second die is stacked above the first die so that the first face of the second die is coupled to the second face of the first die. The electronic assembly further includes a first conductive pathway between one end of the first transmission line and a first connection point at the first face of the first die, a second conductive pathway between one end of the second transmission line and a second connection point at the first face of the first die, and a third conductive pathway between the other ends of the first and second transmission lines.

公开(公告)号：US20230197527A1

公开(公告)日：2023-06-22

申请号：US17554061

申请日：2021-12-17

Applicant: Intel Corporation

Inventor： Richard Geiger ,  Peter Baumgartner ,  Alexander Bechtold ,  Uwe Hodel ,  Richard Hudeczek ,  Walther Lutz ,  Carla Moran Guizan ,  Georgios Panagopoulos ,  Johannes Xaver Rauh ,  Roshini Sachithanandan

IPC: H01L21/8238 ,  H01L23/528 ,  H01L23/535 ,  H01L23/522 ,  H01L27/092

CPC classification number: H01L21/823871 ,  H01L21/823821 ,  H01L23/5286 ,  H01L23/535 ,  H01L23/5226 ,  H01L27/0924

Abstract: IC devices including semiconductor devices isolated by BSRs are disclosed. An example IC device includes a first and a second semiconductor devices, a support structure, and a BSR. The BSR defines boundaries of a first and second section in the support structure. At least a portion of the first semiconductor device is in the first section, and at least a portion of the second semiconductor device is in the second section. The first semiconductor device is isolated from the second semiconductor device by the BSR. Signals from the first semiconductor device would not be transmitted to the second semiconductor device through the support structure. The BSR may be connected to a TSV or be biased. The IC device may include additional BSRs to isolate the first and second semiconductor devices. An BSR may be a power rail used for delivering power.

公开(公告)号：US11424354B2

公开(公告)日：2022-08-23

申请号：US16642867

申请日：2017-09-29

Applicant: Intel Corporation

Inventor： Harald Gossner ,  Peter Baumgartner ,  Uwe Hodel ,  Domagoj Siprak ,  Stephan Leuschner ,  Richard Geiger

IPC: H01L29/778 ,  H01L29/66 ,  H01L29/20

Abstract: A Group III-Nitride (III-N) device structure is provided comprising: a heterostructure having three or more layers comprising III-N material, an anode n+ region and a cathode comprising donor dopants, wherein the anode n+ region and the cathode are on the first layer of the heterostructure and wherein the anode n+ region and the cathode extend beyond the heterostructure, and an anode metal region within a recess that extends through two or more of the layers, wherein the anode metal region is in electrical contact with the first layer, wherein the anode metal region comprises a first width within the recess and a second width beyond the recess, and wherein the anode metal region is coupled with the anode n+ region. Other embodiments are also disclosed and claimed.